Patents by Inventor Susumu Yoshimoto
Susumu Yoshimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144879Abstract: Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including a plurality of stages of sequential circuits. An output signal of a sequential circuit is input to a sequential circuit in the subsequent stage. Before a sequential circuit outputs a signal and after the sequential circuit outputs the signal, the potential of a gate of a transistor included in the sequential circuit is changed in accordance with a clock signal so as to avoid voltage stress application between the gate and a source of the transistor for a long time. The shift register circuit can be applied to a scan line driver circuit of a display apparatus, for example.Type: ApplicationFiled: February 22, 2022Publication date: May 2, 2024Inventors: Satoshi YOSHIMOTO, Susumu KAWASHIMA, Kazunori WATANABE, Tomoaki ATSUMI, Koji KUSUNOKI
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Patent number: 11960185Abstract: Display data of pixels is updated at different timings. A scan line is connected to a first pixel and a second pixel, a first wiring is connected to the first pixel, and a second wiring is connected to the second pixel. In a first period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is updated is supplied to the first wiring, and setting data for setting a state where the display data of the second pixel is updated is supplied to the second wiring. In a second period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is not updated is supplied to the first wiring, and the setting data for setting the state where the display data of the second pixel is updated is supplied to the second wiring.Type: GrantFiled: March 19, 2019Date of Patent: April 16, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kouhei Toyotaka, Satoshi Yoshimoto, Kazunori Watanabe, Susumu Kawashima, Kei Takahashi
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Patent number: 11683019Abstract: A surface acoustic wave device includes a piezoelectric substrate and a pair of interdigital transducer electrodes. The pair of interdigital transducer electrodes include an alternating region as a region where the electrode fingers connected to one busbar and the electrode fingers connected to the other busbar are alternately provided. When a region on an end portion side of the alternating region and a region including distal end portions of the plurality of electrode fingers is referred to as an edge region, a propagation velocity of a surface acoustic wave in the edge region is slower than a propagation velocity of a surface acoustic wave in the alternating region. A propagation velocity of a surface acoustic wave in a busbar region as a region where the busbar is disposed is faster than the propagation velocity of the surface acoustic wave in the alternating region.Type: GrantFiled: November 15, 2019Date of Patent: June 20, 2023Assignee: NDK SAW Devices Co., Ltd.Inventors: Naoto Matsuoka, Makiko Nakamura, Susumu Yoshimoto
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Publication number: 20230178965Abstract: A semiconductor stack includes a first-conductivity-type layer, a quantum well structure, and a second-conductivity-type layer. The first-conductivity-type layer, the quantum well structure, and the second-conductivity-type layer are stacked in this order. The quantum well structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the first semiconductor layer and the third semiconductor layer, compositions of the first semiconductor layer and the third semiconductor layer are changed such that a bandgap decreases toward the second semiconductor layer. Transition of an electron is possible between a conduction band of each of the first semiconductor layer and the third semiconductor layer and a valence band of the second semiconductor layer.Type: ApplicationFiled: October 27, 2022Publication date: June 8, 2023Inventors: Takuma FUYUKI, Susumu YOSHIMOTO
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Publication number: 20230036079Abstract: A vertical cavity surface-emitting laser configured to emit laser light having a wavelength of 830 nm to 910 nm includes a substrate having a main surface including GaAs, a first distributed Bragg reflector, an active layer, and a second distributed Bragg reflector. The substrate, the first distributed Bragg reflector, the active layer, and the second distributed Bragg reflector are arranged in a first axis direction intersecting the main surface. The main surface has an off angle of 6° or more with respect to a (100) plane. The active layer includes InxAlyGa1-x-yAs (0<x<1, 0?y<1). The active layer has a strain. An absolute value of the strain is 0.5% to 1.4%.Type: ApplicationFiled: July 8, 2022Publication date: February 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takamichi SUMITOMO, Kei FUJII, Suguru ARIKATA, Takeshi AOKI, Susumu YOSHIMOTO
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Publication number: 20220320830Abstract: A surface-emitting laser includes a lower DBR layer, a cavity layer, and an upper DBR layer that are stacked in this order on top of a substrate, wherein the lower DBR layer has a first DBR layer, a contact layer, and a second DBR layer that are stacked in this order on top of the substrate, wherein the first DBR layer and the second DBR layer each include a plurality of first layers and a plurality of second layers that are alternately stacked, wherein the first layers and the second layers are each a semiconductor layer including aluminum, wherein a composition ratio of the aluminum of each first layer is lower than a composition ratio of the aluminum of each second layer, and wherein the second DBR layer includes 12 or more and 20 or fewer pairs of the first layers and the second layers.Type: ApplicationFiled: March 31, 2020Publication date: October 6, 2022Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takeshi AOKI, Susumu YOSHIMOTO
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Patent number: 10714640Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.Type: GrantFiled: January 24, 2017Date of Patent: July 14, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Suguru Arikata, Susumu Yoshimoto, Katsushi Akita
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Publication number: 20200162052Abstract: A surface acoustic wave device includes a piezoelectric substrate and a pair of interdigital transducer electrodes. The pair of interdigital transducer electrodes include an alternating region as a region where the electrode fingers connected to one busbar and the electrode fingers connected to the other busbar are alternately provided. When a region on an end portion side of the alternating region and a region including distal end portions of the plurality of electrode fingers is referred to as an edge region, a propagation velocity of a surface acoustic wave in the edge region is slower than a propagation velocity of a surface acoustic wave in the alternating region. A propagation velocity of a surface acoustic wave in a busbar region as a region where the busbar is disposed is faster than the propagation velocity of the surface acoustic wave in the alternating region.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: Naoto MATSUOKA, Makiko NAKAMURA, Susumu YOSHIMOTO
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Patent number: 10594110Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.Type: GrantFiled: November 13, 2018Date of Patent: March 17, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
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Publication number: 20200028328Abstract: A vertical cavity surface emitting laser includes an active layer having a quantum well structure, a first laminate for a first distributed Bragg reflector, and a first spacer region provided between the active layer and the first laminate. A barrier layer of the quantum well structure includes a first compound semiconductor containing aluminum as a group m constituent element. The first spacer region includes a second compound semiconductor having a larger aluminum composition than the first compound semiconductor. A concentration of first dopant in the first laminate is larger than a concentration of the first dopant in the first portion of the first spacer region. The concentration of the first dopant in the first portion of the first spacer region is larger than a concentration of the first dopant in the second portion of the first spacer region.Type: ApplicationFiled: July 18, 2019Publication date: January 23, 2020Applicant: Sumitomo Electric Industries, LTD.Inventors: Suguru ARIKATA, Susumu YOSHIMOTO, Takamichi SUMITOMO, Kei FUJII
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Patent number: 10326034Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.Type: GrantFiled: January 24, 2017Date of Patent: June 18, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Suguru Arikata, Takuma Fuyuki, Susumu Yoshimoto, Takashi Kyono, Katsushi Akita
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Publication number: 20190148914Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.Type: ApplicationFiled: November 13, 2018Publication date: May 16, 2019Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
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Publication number: 20190044306Abstract: A vertical cavity surface emitting laser includes: an active layer; a first laminate for a first distributed Bragg reflector; and a first intermediate layer disposed between the active layer and the first laminate. The first intermediate layer has first and second portions. The first laminate, the first and second portions of the first intermediate layer, and the active layer are arranged along a direction of a first axis. The first laminate and the first portion of the first intermediate layer each include a first dopant. The active layer has a first-dopant concentration of less than 1×1016 cm?3. The first portion of the first intermediate layer has a first-dopant concentration smaller than that of the first laminate. The second portion of the first intermediate layer has a first-dopant concentration smaller than that of the first portion of the first intermediate layer.Type: ApplicationFiled: July 30, 2018Publication date: February 7, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Toshiyuki TANAHASHI, Takashi ISHIZUKA, Susumu YOSHIMOTO, Takamichi SUMITOMO, Koji NISHIZUKA, Kei FUJI, Suguru ARIKATA
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Publication number: 20190044010Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.Type: ApplicationFiled: January 24, 2017Publication date: February 7, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Suguru ARIKATA, Takuma FUYUKI, Susumu YOSHIMOTO, Takashi KYONO, Katsushi AKITA
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Publication number: 20190035954Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.Type: ApplicationFiled: January 24, 2017Publication date: January 31, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Suguru ARIKATA, Susumu YOSHIMOTO, Katsushi AKITA
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Publication number: 20180315890Abstract: A semiconductor layered body includes: a plurality of protrusions having first main surfaces along a reference plane and protruding from the reference plane; and a first semiconductor layer disposed at a side of the plurality of protrusions opposite to the first main surfaces so as to connect the plurality of protrusions to one another. Each of the protrusions is composed of a group III nitride that has a dislocation density of less than or equal to 1×108 cm?3, that is expressed by a composition formula of AlxGa1-xN, and that satisfies 0?x<1. The first semiconductor layer is composed of a group III nitride that has a dislocation density of less than or equal to 1×109 cm?3, that is expressed by a composition formula of AlyGa1-yN, and that satisfies 0<y?1.Type: ApplicationFiled: October 28, 2016Publication date: November 1, 2018Applicants: Sumitomo Electric Industries, Ltd., RIKENInventors: Susumu YOSHIMOTO, Masaki UENO, Katsushi AKITA, Yoshiyuki YAMAMOTO, Hideki HIRAYAMA
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Publication number: 20170338376Abstract: A layered body includes: a plate-like supporting body having a supporting main surface; and a plurality of projection portions disposed on the supporting main surface, each of the plurality of projection portions being composed of a group III nitride and having a dislocation density of not more than 1×108 cm?3. The projection portion preferably has a polygonal planar shape. The projection portion preferably has a plate-like shape. Preferably, each of the plurality of projection portions has a main surface opposite to the supporting body and corresponding to a {0001} plane of the group III nitride of the projection portions, and the adjacent projection portions of the plurality of projection portions have end surfaces facing each other and corresponding to a {11-20} plane of the group III nitride of the projection portions.Type: ApplicationFiled: October 28, 2016Publication date: November 23, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Susumu YOSHIMOTO, Katsushi AKITA, Masaki UENO, Yoshiyuki YAMAMOTO
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Patent number: 9607905Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.Type: GrantFiled: September 2, 2015Date of Patent: March 28, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
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Publication number: 20160372609Abstract: A Schottky barrier diode includes a semiconductor layer, a Schottky electrode on a first main surface of the semiconductor layer, the Schottky electrode being in Schottky contact with the semiconductor layer, and an ohmic electrode on a second main surface of the semiconductor layer opposite the first main surface, the ohmic electrode being in ohmic contact with the semiconductor layer. The semiconductor layer contains gallium nitride or silicon carbide. The semiconductor layer includes a drift layer. The drift layer has a thickness of 2 ?m or less.Type: ApplicationFiled: June 17, 2016Publication date: December 22, 2016Inventors: Makoto Kiyama, Masaya Okada, Susumu Yoshimoto, Masaki Ueno
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Publication number: 20160064292Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Mitsuhiko Sakai, Susumu Yoshimoto