Abstract: A quadrature switching mixer is provided for mixing a received RF signal and a local oscillator signal, while rejecting an image signal associated with the RF signal. Input signal components in quadrature, that is, I and Q input components derived from the received RF signal, are respectively coupled through first and second input paths to corresponding commuting switches in a configuration of switches. Each of the switches operates to multiply respective quadrature components of RF and local oscillator signals to provide quadrature output signal components. A unidirectional device, such as a buffer amplifier included in a signal splitter, is placed in each input path to prevent any portion of an output signal component from leaking backward through one of the input paths to the other input path, and thus to the other output signal component.

Abstract: A method and apparatus for minimizing harmonic content in a digital signal driver circuit are disclosed. A digital input signal applied to an input node generates a corresponding digital output in a circuit with two or more MOS devices in cascode connection with each other. The slew rate of leading or trailing edge transitions associated with the output signal are controlled using one or more parasitic capacitances associated with the fabrication of two or cascode connected MOS devices. The two or more cascode connected MOS devices may further each have gate electrodes connected to a fixed potential so as to minimize the harmonic content. A control signal may further be applied to each gate electrode to turn off a leakage current path between source and drain electrodes. Harmonics may further be controlled by limiting a conductance between gate electrodes and fixed potentials using an active or passive device.

Abstract: An electrical oscillator circuit (301, 302) comprising: a resonator (303) comprised in the first subcircuit (301); and an active device (309) comprised in the second subcircuit (302) connected to energize the resonator (303) to provide an oscillating electrical signal transmitted as a differential signal via electrical conductors (306, 307) to the second subcircuit (302). The oscillator is characterized in that the second subcircuit (302) comprises means (311, 312, 313, 314) for receiving the differential signal transmitted via the electrical conductors (306, 307) and converting the differential signal to a single-ended signal with reference to the signal ground reference (G2) of the second subcircuit (302). Thereby a noise robust oscillator signal is provided with the use of very few components. Particularly suitable for oscillators embodied in an integrated circuit with the resonator mounted on a printed circuit board, PCB. And an integrated circuit.

Abstract: An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

Abstract: An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

Abstract: A method and system for increasing the compression point of a receiver by deriving a feedback signal from mixer output signals. The feedback signal prevents the receiver from going into compression on strong out-of-band or blocking signals, while enhancing the receiver gain at the desired frequency. The desired frequency coincides with the local oscillator (LO) signal and is therefore particularly applicable for, but not limited to, homodyne receivers where selectivity can be made quite narrowband. Since the selectivity is coupled to the LO, a tunable receiver may be achieved that enables selectivity over a wide range of input frequencies.

Abstract: A method and apparatus for minimizing harmonic content in a digital signal driver circuit are disclosed. A digital input signal applied to an input node generates a corresponding digital output in a circuit with two or more MOS devices in cascode connection with each other. The slew rate of one or more edge transitions associated with the output signal are controlled using one or more parasitic capacitances associated with the fabrication of two or more cascode connected MOS devices. The two or more cascode connected MOS devices may further each have gate electrodes connected to a fixed potential so as to minimize said harmonic content. A control signal may further be applied to each gate electrode to turn off a leakage current path between source and drain electrodes. Harmonics may further be controlled by limiting a conductance between gate electrodes and fixed potentials using an active or passive device.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: A short-range radio transmitter of a communication device comprising a short-range radio and a long-range radio is controlled to delay packets which are scheduled to be transmitted at the same time as a long-range transmitter of the long-range radio commences or discontinues to transmit. A frequency synthesizer of the short-range radio is thereby not affected by a change in the power supply voltage which otherwise occurs at these moments due to transmission with high power by the long-range transmitter.

Abstract: Methods and apparatus for performing synchronization and DC-offset compensation in FM transmission systems significantly reduce the overhead associated with transmitting a conventional digital preamble at the start of each of a succession of transmitted digital data packets. According to exemplary embodiments, a multi-part digital preamble includes a short, substantially DC-free leading part followed by a code-protected synchronization part which is not necessarily substantially DC-free. The leading part provides for coarse DC offset estimation and synchronization, while the coded synchronization part carries timing and/or other useful information which can be unique for each packet. One or more substantially DC-free trailing parts follow the synchronization part, or are included in the synchronization part itself, and provide for fine tuning of the DC-offset estimate.

Abstract: Method and system are disclosed for providing an improved linearity Gilbert mixer. The Gilbert mixer of the present invention includes a conventional mixer core coupled to a high linearity, multistage amplifier. The multistage amplifier includes two or more transistor stages connected together in a global feedback arrangement. The global feedback provides a greater loop gain for the amplifier than the local feedback arrangement, thereby increasing the linearity of the amplifier. In addition, having more than one transistor stage in the amplifier serves to increase the isolation of the RF input signal from the LO input signal. Furthermore, by providing parallel output stages in the multistage amplifier, several mixer cores may be driven from the same source while sharing the feedback mechanism.

Abstract: A quadrature switching mixer is provided for mixing a received RF signal and a local oscillator signal, while rejecting an image signal associated with the RF signal. Input signal components in quadrature, that is, I and Q input components derived from the received RF signal, are respectively coupled through first and second input paths to corresponding commuting switches in a configuration of switches. Each of the switches operates to multiply respective quadrature components of RF and local oscillator signals to provide quadrature output signal components. A unidirectional device, such as a buffer amplifier included in a signal splitter, is placed in each input path to prevent any portion of an output signal component from leaking backward through one of the input paths to the other input path, and thus to the other output signal component.

Abstract: An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

Abstract: The invention relates to an integrated gyrator structure, in which each transistor in the gyrator core (preferably MOS devices) has series feedback associated therewith. This allows for compensation over a large bandwidth of the effects of channel delay in the MOS transistors.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3 , R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: Transmission power in a frequency-hopping radio system that transmits packets from a sending radio unit to a receiving radio unit, wherein each packet includes an address designating the receiving radio unit, is controlled by measuring received signal strength of packets whose addresses were successfully received in the receiving radio unit, regardless of whether other portions of the respective packets were successfully received. An average signal strength value is generated from the received signal strength measurements. The mathematical difference between the average signal strength value and a target value associated with the receiving radio unit is then determined and used as a basis for deciding whether to send a power control message from the receiving radio unit to the sending radio unit.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: The invention relates to a filter circuit and a method for making a filter circuit comprising at least one gyrator core section (GCi) having four inverters mutually connected in a loop configuration between a pair of input terminals (i—1; i—2) and a pair of output terminals (o—1; o—2). At least one common mode feedback section (CMIi, CMOi) is provided between the pair of input terminals and/or the pair of output terminals. The common mode feedback section comprises two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallelly between the input terminals or the output terminals. The inverters may be constituted by a MOS, CMOS or BiCMOS or bipolar transistor.

Abstract: An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.