Abstract: A proximity detector for use in a mobile telephone apparatus, wherein the phone has at least a microphone (1) and a loudspeaker (5) operatively connected to signal processing means (2,3,4). The proximity detector comprises data processing and control means (6) including means for controlling the signal processing means (3,4) in order to activate the loudspeaker for reproducing an acoustic control signal, correlating means for correlating the control signal received directly (Ddirect) by the microphone (1) and the control signal being reflected (D1+D2) from a user (13) of the phone (9) and then received by the microphone (1) for determining the distance (D1≈D2) between the phone (9) and the user (13), and signal level control means for controlling the signal processing means (3,4) in order to varying the signal level of an audible signal reproduced by the loudspeaker (5) proportionally to the determined distance (D1≈D2) between the phone (9) and the user (13).

Abstract: Integrated circuits, for example, gyrator circuits include transistors that are preferably MOS devices and that are provided with series feedback networks, which compensate for the effects of channel delay in the MOS devices.

Abstract: A method of estimating a DC offset value of a signal includes estimating a DC offset value of a preamble part of the signal using a pair of diodes (D1, D2) and a resistor (R) connected in parallel. During receipt of the data part of the signal, the diode pair (D1, D2) is switched out of the circuit by a switch (SW). During reception of the data part, the DC level is estimated using a low pass filter (R,C).

Abstract: A communications terminal having a receiver and a method therefor is provided that substantially removes a known interferer from a digitally translated intermediate frequency signal. More specifically, the receiver includes an antenna for receiving a signal, and at least one combination of a mixer and filter for translating in the analog domain the signal to the intermediate frequency signal while maintaining separation from baseband. The receiver also includes a digitizer for digitally translating the intermediate frequency signal containing the known interferer from the analog domain into the digital domain, and an interference cancellation system for removing the known interferer from the digitally translated intermediate frequency signal by utilizing either a DC offset compensator or a correlator compensator.

Abstract: In a radio front-end circuit having at least two amplifier-mixer cascades, the amplifiers are switched on or off via the mixers. By switching between the amplifier-mixer cascades, the power consumption is lowered.

Abstract: In a radio front-end circuit having at least two amplifier-mixer cascades, the amplifiers are switched on or off via the mixers. By switching between the amplifier-mixer cascades, the power consumption is lowered.

Abstract: A dual-radio communication apparatus (100) has a first radio device (110), such as a Bluetooth radio, for use in a first frequency band, and a second radio device (120), such as a Globalstar satellite radio, for use in a second frequency band, which is proximate to the first frequency band. The communication apparatus also has a controller coupled to the first and second radio devices. The first radio device may comprise a frequency-hopping spread-spectrum transmitter. Moreover, the first radio device (110) has a first operating mode employing a first frequency range. The first radio device also has a second operating mode employing a second frequency range, which is smaller than the first frequency range. The controller is adapted to set the first radio device in its second operating mode, when the second radio device (120) is in operation, and otherwise set the first radio device in its first operating mode.

Abstract: A frequency modulated signal demodulator circuit includes a phase shift element and a time delay element which operate on an input signal (V_IF). The phase shift element and the time delay element are provided by a gyrator component (14, 16, 20).

Abstract: The invention relates to a filter circuit and a method for making a filter circuit comprising at least one gyrator core section (GCi) having four inverters mutually connected in a loop configuration between a pair of input terminals (i—1; i—2) and a pair of output terminals (o—1; o—2). At least one common mode feedback section (CMIi, CMOi) is provided between the pair of input terminals and/or the pair of output terminals. The common mode feedback section comprises two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallelly between the input terminals or the output terminals. The inverters may be constituted by a MOS, CMOS or BiCMOS or bipolar transistor.

Abstract: A communications terminal having a receiver and a method is provided that substantially removes a known interferer from a digitally translated intermediate frequency signal. More specifically, the receiver includes an antenna for receiving a signal, and at least one combination of a mixer and filter for translating in the analog domain the signal to the intermediate frequency signal while maintaining separation from baseband. The receiver also includes a digitizer for digitally translating the intermediate frequency signal containing the known interferer from the analog domain into the digital domain, and an interference cancellation system for removing the known interferer from the digitally translated intermediate frequency signal by utilizing either a DC offset compensator or a correlator compensator.

Abstract: A demodulator circuit for demodulating a frequency modulated input, which includes a detector (14) that is operable to produce a demodulated signal from an incoming frequency modulated signal. A tuning circuit (19) is connected to the detector and operable to vary the frequency response characteristics of the detector. An auxiliary detector (25, 26) is connected to receive a reference frequency signal and to provide an auxiliary tuning signal to the detector on the basis of detection of the reference frequency signal.

Abstract: A radio communication system that utilizes an available frequency spectrum that is divided up into a plurality of channels to be used by the radio communication system is operated in accordance with a frequency hopping strategy that permits a user to simultaneously utilize more than one channel during each hop period, wherein it is permissible, but not mandatory, for at least one of the channels utilized by the user during a first hop period to again be used by the user during an immediately following second hop period, so long as at least one of the channels utilized by the user during the second hop period is different from all of the channels utilized by the user during the first hop period. In some embodiments, the number of channels simultaneously utilized by any one user need not be the same as the number of channels simultaneously utilized by any other user.

Abstract: A demodulator circuit for demodulating a frequency modulated input signal includes a filter (12) for receiving an incoming input signal and for providing a filtered output signal, a detector (16) for receiving the filtered output signal, and for producing a demodulated output signal therefrom, a tuning circuit (18, 20) which is operable to introduce a test signal into the demodulator circuit in the absence of an incoming input signal, and to vary the frequency response characteristics of at least one of the filter and detector in response to the test signal.

Abstract: An FM demodulator circuit includes a filter (10) and a detector (14) for receiving a frequency modulated input signal and for providing a demodulated output signal. A tuning circuit (19) is provided for tuning the frequency characteristics of the filter and of the detector. A DC offset estimator (18) is connected to the output of the detector to produce an offset signal representing the estimated DC offset of the demodulated output signal, and to provide the offset signal to the tuning circuit. The tuning circuit is operable to tune the frequency characteristics of the filter and detector in dependence upon the offset signal.

Abstract: An antenna switch for selectively connecting an output differential signal pair of an output power amplifier to a single-ended signal of an antenna when transmitting and selectively connecting an input differential signal pair of a low noise input amplifier to the single-ended signal of the antenna when receiving. A first balun having a single ended-signal connected to an antenna connects a first and second output differential signal to a power output amplifier. A second balun having a single-ended signal connected to the antenna connects a first and second input differential signal to a low noise input amplifier. A first diode selectively shorts the first output differential signal to the second output differential signal of the first balun when receiving and a second diode selectively shorts the first input differential signal to the second input differential signal of the second balun when transmitting.

Abstract: An amplifier (10) is disclosed including circuity for improving the amplifiers performance, particularly the common mode rejection of differential amplifiers, by adding the amplifier input signal to the power supply signals which power the amplifier. Voltage dividers (42, 44) are connected between the amplifier output (16) and each of the two power supply rails (26, 28). Each divider includes resistors (46, 48; 50, 52) selected so that the amplifier output is divided down by a factor equal to the gain of the amplifier. The junction signals (V.sub.J1, V.sub.J2) provided by the two voltage dividers thus each includes a component equal to the input signal. The junction voltages are applied to the amplifier power input terminals (18, 20) by respective transistors (60, 62), each connected in a voltage follower arrangement. One embodiment (FIG. 4) incorporates a servo amplifier (100) for DC offset stabilization.

Abstract: A low noise amplifier circuit (FIGS. 4 and 5) is disclosed including plural differential amplifiers having their inputs and outputs connected to common input and output lines (50, 52; 54, 56). In the disclosure, each differential amplifier is comprised of a pair of bipolar junction transistors (40, 42; 58, 60; 64, 66) of the same type. Parallel connecting of the differential amplifiers in the disclosed fashion reduces the Johnson noise introduced by the base spreading resistances of the individual transistors. Since differential amplifiers, per se, are connected in parallel rather than their component transistors, thermal runaway is not a problem.

Abstract: An equalization amplifier (30) is disclosed which includes two amplifier stages (32, 34) connected in cascade. The first amplifier stage (32) includes a low pass filter amplifier (40) having a pole frequency of F1 and a feed forward path (36) bypassing the low pass filter amplifier. The feed forward path provides the input signal to an adder circuit (42) where it is added to the output of the low pass filter amplifier. The effect of this addition is to provide the first amplifier with a zero frequency of F2, where F2 is greater than F1. The resulting sum signal is applied to the second amplifier stage (34) which also has a low pass filter characteristic. The second filter has a pole frequency of F3, where F3 is greater than F2. The equalization amplifier is particularly useful for providing RIAA equalization of phono cartridge output signals.