Patents by Inventor Swee Kah Lee
Swee Kah Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176222Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.Type: GrantFiled: November 29, 2021Date of Patent: December 24, 2024Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Thorsten Meyer, Chan Lam Cha, Wern Ken Daryl Wee, Chee Hong Lee, Swee Kah Lee, Norliza Morban, Khay Chwan Andrew Saw
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Publication number: 20240312956Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.Type: ApplicationFiled: March 17, 2023Publication date: September 19, 2024Inventors: Pei Luan Pok, Swee Kah Lee, Soon Lock Goh, Chee Hong Lee, Samsun Paing, Chee Chiew Chong
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Publication number: 20240274563Abstract: A solder structure and method is disclosed. In one example, the solder structure includes a solder material, and a coating which at least partially coats the solder material and is configured for protecting the solder material against solder spreading. The coating is at least partially disrupted when establishing a solder connection between the solder material and a solderable structure.Type: ApplicationFiled: January 18, 2024Publication date: August 15, 2024Applicant: Infineon Technologies AGInventors: Hock Heng CHONG, Hui Khin TAN, Chee Yang NG, Swee Kah LEE
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Publication number: 20240215208Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.Type: ApplicationFiled: December 23, 2022Publication date: June 27, 2024Inventors: Chee Yang NG, Swee Kah LEE
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Publication number: 20240213035Abstract: A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Inventors: Chew Yeek Lau, Swee Kah Lee, Fong Mei Lum, Kon Hoe Chin
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Publication number: 20240186152Abstract: A method of processing chips is disclosed. In one example, the method comprises encapsulating mutually spaced chips by an encapsulant comprising a locally curable material. The encapsulated chips with the encapsulant are separated into a plurality of encapsulated chip sections by locally curing selectively portions of the encapsulant covering at least a portion of the chips without curing other portions of the encapsulant apart from the encapsulated chip sections.Type: ApplicationFiled: November 10, 2023Publication date: June 6, 2024Applicant: Infineon Technologies AGInventors: Roslie Saini BAKAR, Hock Heng CHONG, Swee Kah LEE, Wei Wei YONG
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Publication number: 20240006260Abstract: A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.Type: ApplicationFiled: May 8, 2023Publication date: January 4, 2024Applicant: Infineon Technologies AGInventors: Chee Hong LEE, Soon Lock GOH, Chai Chee LEE, Swee Kah LEE, Luay Kuan ONG, Chee Voon TAN
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Publication number: 20230335516Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.Type: ApplicationFiled: March 23, 2023Publication date: October 19, 2023Applicant: Infineon Technologies AGInventors: Chee Yang NG, Chew Yeek LAU, Swee Kah LEE, Joseph Victor SOOSAI PRAKASAM, Hui Khin TAN
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Patent number: 11791169Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.Type: GrantFiled: August 14, 2020Date of Patent: October 17, 2023Assignee: INFINEON TECHNOLOGIES AGInventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
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Patent number: 11682644Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.Type: GrantFiled: June 29, 2021Date of Patent: June 20, 2023Assignee: Infineon Technologies AGInventors: Swee Kah Lee, Sook Woon Chan, Fong Mei Lum, Joachim Mahler, Muhammad Muhammat Sanusi
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Publication number: 20230170226Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Inventors: Chau Fatt Chiang, Thorsten Meyer, Chan Lam Cha, Wern Ken Daryl Wee, Chee Hong Lee, Swee Kah Lee, Norliza Morban, Khay Chwan Andrew Saw
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Patent number: 11469161Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.Type: GrantFiled: August 27, 2020Date of Patent: October 11, 2022Assignee: Infineon Technologies AGInventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
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Publication number: 20220278085Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.Type: ApplicationFiled: February 22, 2022Publication date: September 1, 2022Applicant: Infineon Technologies AGInventors: Chau Fatt CHIANG, Paul Armand Asentista CALO, Chan Lam CHA, Kok Yau CHUA, Chee Hong LEE, Swee Kah LEE, Theng Chao LONG, Jayaganasan NARAYANASAMY, Khay Chwan Andrew SAW
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Publication number: 20220199478Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.Type: ApplicationFiled: December 16, 2021Publication date: June 23, 2022Inventors: Si Hao Vincent Yeo, Chan Lam Cha, Ying Dieh Cheong, Chau Fatt Chiang, Cher Hau Danny Koh, Wern Ken Daryl Wee, Swee Kah Lee, Desmond Jenn Yong Loo, Fortunato Lopez, Norliza Morban, Khay Chwan Andrew Saw, Sock Chien Tey, Mei Yong Wang
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Patent number: 11302613Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.Type: GrantFiled: July 9, 2020Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
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Patent number: 11289436Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.Type: GrantFiled: May 28, 2020Date of Patent: March 29, 2022Assignee: Infineon Technologies Austria AGInventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
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Patent number: 11274984Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: GrantFiled: June 2, 2020Date of Patent: March 15, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20220068773Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.Type: ApplicationFiled: August 27, 2020Publication date: March 3, 2022Inventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
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Publication number: 20220005778Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.Type: ApplicationFiled: June 29, 2021Publication date: January 6, 2022Inventors: Swee Kah Lee, Sook Woon Chan, Fong Mei Lum, Joachim Mahler, Muhammad Muhammat Sanusi
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Patent number: 11174152Abstract: An embodiment device includes a body structure having an interior cavity, a control chip disposed on a first interior surface of the interior cavity, and a sensor attached, at a first side, to a second interior surface of the interior cavity opposite the first interior surface. The sensor has a mounting pad on a second side of the sensor that faces the first interior surface, and the sensor is vertically spaced apart from the control chip by an air gap, with the sensor is aligned at least partially over the control chip. The device further includes an interconnect having a first end mounted on the mounting pad, the interconnect extending through the interior cavity toward the first interior surface, and the control chip is in electrical communication with the sensor by way of the interconnect.Type: GrantFiled: October 22, 2019Date of Patent: November 16, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Swee Kah Lee, Chee Yang Ng