Patents by Inventor Swee Kah Lee

Swee Kah Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006260
    Abstract: A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.
    Type: Application
    Filed: May 8, 2023
    Publication date: January 4, 2024
    Applicant: Infineon Technologies AG
    Inventors: Chee Hong LEE, Soon Lock GOH, Chai Chee LEE, Swee Kah LEE, Luay Kuan ONG, Chee Voon TAN
  • Publication number: 20230335516
    Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 19, 2023
    Applicant: Infineon Technologies AG
    Inventors: Chee Yang NG, Chew Yeek LAU, Swee Kah LEE, Joseph Victor SOOSAI PRAKASAM, Hui Khin TAN
  • Patent number: 11791169
    Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 17, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
  • Patent number: 11682644
    Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: June 20, 2023
    Assignee: Infineon Technologies AG
    Inventors: Swee Kah Lee, Sook Woon Chan, Fong Mei Lum, Joachim Mahler, Muhammad Muhammat Sanusi
  • Publication number: 20230170226
    Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Chau Fatt Chiang, Thorsten Meyer, Chan Lam Cha, Wern Ken Daryl Wee, Chee Hong Lee, Swee Kah Lee, Norliza Morban, Khay Chwan Andrew Saw
  • Patent number: 11469161
    Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 11, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
  • Publication number: 20220278085
    Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 1, 2022
    Applicant: Infineon Technologies AG
    Inventors: Chau Fatt CHIANG, Paul Armand Asentista CALO, Chan Lam CHA, Kok Yau CHUA, Chee Hong LEE, Swee Kah LEE, Theng Chao LONG, Jayaganasan NARAYANASAMY, Khay Chwan Andrew SAW
  • Publication number: 20220199478
    Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Inventors: Si Hao Vincent Yeo, Chan Lam Cha, Ying Dieh Cheong, Chau Fatt Chiang, Cher Hau Danny Koh, Wern Ken Daryl Wee, Swee Kah Lee, Desmond Jenn Yong Loo, Fortunato Lopez, Norliza Morban, Khay Chwan Andrew Saw, Sock Chien Tey, Mei Yong Wang
  • Patent number: 11302613
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Patent number: 11289436
    Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
  • Patent number: 11274984
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 15, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
  • Publication number: 20220068773
    Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Inventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
  • Publication number: 20220005778
    Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.
    Type: Application
    Filed: June 29, 2021
    Publication date: January 6, 2022
    Inventors: Swee Kah Lee, Sook Woon Chan, Fong Mei Lum, Joachim Mahler, Muhammad Muhammat Sanusi
  • Patent number: 11174152
    Abstract: An embodiment device includes a body structure having an interior cavity, a control chip disposed on a first interior surface of the interior cavity, and a sensor attached, at a first side, to a second interior surface of the interior cavity opposite the first interior surface. The sensor has a mounting pad on a second side of the sensor that faces the first interior surface, and the sensor is vertically spaced apart from the control chip by an air gap, with the sensor is aligned at least partially over the control chip. The device further includes an interconnect having a first end mounted on the mounting pad, the interconnect extending through the interior cavity toward the first interior surface, and the control chip is in electrical communication with the sensor by way of the interconnect.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 16, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Swee Kah Lee, Chee Yang Ng
  • Patent number: 11081417
    Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
  • Publication number: 20210050227
    Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Inventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
  • Patent number: 10914018
    Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Norbert Pielmeier, Chin Yung Lai, Swee Kah Lee, Muhammad Muhammat Sanusi, Evelyn Napetschnig, Nurfarena Othman, Siew Ching Seah
  • Publication number: 20210025774
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Application
    Filed: June 2, 2020
    Publication date: January 28, 2021
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
  • Publication number: 20210020547
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Publication number: 20210020550
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan