Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

Abstract: Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates are disclosed. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof.

Abstract: Collars, support structures, or forms for protruding conductive structures include apertures or receptacles through which the conductive structure may extend. The aperture or receptacle may be configured to contact a surface of the conductive structure, and even to define a shape of at least a portion of the conductive structure. Each collar, support structure, or form may include a plurality of adjacent, mutually adhered regions.

Abstract: One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. Upon assembly of the semiconductor device component face-down upon a higher-level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher-level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher-level substrate to maintain a substantially parallel relation therebetween. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher-level substrate. The stabilizers may be preformed structures or fabricated on the surface of the semiconductor device component, such as by way of a stereolithographic method.

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: Stabilizers for placement on a surface of a semiconductor device component and methods for fabricating and placing the stabilizers on semiconductor device components. Upon assembly of the semiconductor device component face down upon a higher level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher level substrate to prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The stabilizers may be either preformed structures or formed on the surface of the semiconductor device component. A stereolithographic method of fabricating the stabilizers is disclosed.

Abstract: A method and apparatus for achieving a consistent depth of immersion of a semiconductor element into an exposed surface of an adhesive material pool when applying the adhesive material, conductive or non-conductive, to the semiconductor element or portion thereof. The consistent depth of immersion is defined by a stop which is attached to a reservoir used to form the adhesive material pool, attached to a stencil which is used in conjunction with the reservoir to form a level upper surface on the adhesive material, or operates independently from the reservoir and/or stencil.

Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be pre-formed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

Abstract: Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates are disclosed. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.