Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for-positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof.

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

Abstract: An integrated circuit device comprising a semiconductor connection component attached to a semiconductor die with an electrically conductive adhesive material. The integrated circuit device is structured with a semiconductor connection component having a first portion horizontally offset from a second portion, the first portion of the semiconductor connection component carrying the adhesive material. The semiconductor connection component may be a lead frame element having a lead finger. The semiconductor connection component with the electrically conductive adhesive material attached to the first portion thereof is a terminal such as a bond pad on a surface of a semiconductor die. The electrically conductive adhesive material is precisely applied in a simple manner, little adhesive material is wasted, and a one-step electrical/mechanical connection to bond pads of the die is provided.

Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: A leadframe including offsets extending from a major plane thereof The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: The invention is directed to the application of viscous materials, such as the adhesives used in LOC die attach processes, to a lead frame by forming a film of viscous material and then bringing a portion of the lead frame and the film of viscous material into contact with one another. In one exemplary embodiment of the method of the invention, the viscous material is drop dispensed, sprayed, pumped or otherwise placed on a carrier surface, the material is spread to a uniform film thickness and then brought into contact with the die attach portion of the lead frame. One embodiment of the apparatus for applying the viscous material includes (1) a carrier surface, (2) a plurality of orifices in fluid communication with the carrier surface, and (3) a pump for pumping the viscous material through the orifices to the carrier surface. The apparatus may also include a metering blade for spreading the material to a uniform film thickness over the carrier surface.

Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: A leadframe including offsets extending from a major plane thereof The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: Stabilizers for placement on a surface of a semiconductor device component and methods for fabricating placing the stabilizers on semiconductor device components. Upon assembly of the semiconductor device component face down upon a higher level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher level substrate to prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The stabilizers may be either preformed structures or formed on the surface of the semiconductor device component. A stereolithographic method of fabricating the stabilizers is disclosed.

Abstract: A method and apparatus for achieving a consistent depth of immersion of a semiconductor element into an exposed surface of an adhesive material pool when applying the adhesive material, conductive or non-conductive, to the semiconductor element or portion thereof. The consistent depth of immersion is defined by a stop which is attached to a reservoir used to form the adhesive material pool, attached to a stencil which is used in conjunction with the reservoir to form a level upper surface on the adhesive material, or operates independently from the reservoir and/or stencil.

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

Abstract: A method and apparatus for achieving a consistent depth of immersion of a semiconductor element into an exposed surface of an adhesive material pool when applying the adhesive material, conductive or non-conductive, to the semiconductor element or portion thereof. The consistent depth of immersion is defined by a stop which is attached to a reservoir used to form the adhesive material pool, attached to a stencil which is used in conjunction with the reservoir to form a level upper surface on the adhesive material, or operates independently from the reservoir and/or stencil.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: An integrated circuit die test apparatus adapted to minimize damage to solder balls in a ball grid array. The apparatus includes a plurality of flexible pillars or other flexible support structures. The pillars may be formed of an electrically conductive polymer or other material, or formed of polymer and coated with a metallic substance. One or more pillars may be used to contact each solder ball during burn-in. The pillars flex under contact with the solder balls, and spring back upon disengagement. The support structures may be rectangular or wedge-shaped.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high Temperatures or changes in temperature.

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.