Patents by Inventor Sylvain Maitrejean

Sylvain Maitrejean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11810789
    Abstract: A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 7, 2023
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay Reboh, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
  • Patent number: 11694991
    Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: July 4, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank Fournel, Emilie Bourjot, Séverine Cheramy, Sylvain Maitrejean, Loic Sanchez
  • Patent number: 11688811
    Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: June 27, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
  • Patent number: 11424121
    Abstract: A method for forming a layer by cycled epitaxy includes at least one sequence of steps each having a first epitaxial deposition forming a first growth layer portion having a first thickness on a first monocrystalline pattern and a second growth layer portion having a second thickness on a second non-monocrystalline pattern, the second thickness being greater than the first thickness, and a second epitaxial deposition forming a first sacrificial layer portion having a third thickness on the first growth layer portion and a second sacrificial layer portion having a fourth thickness on the second growth layer portion. The first and second growth layer portions have an additional element content, greater than the additional element content present in the first and second sacrificial layer portions. The sequence also includes etching the whole of the third and fourth thicknesses and stopping before having consumed the whole of the first thickness.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 23, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Mazzocchi, Sylvain Maitrejean
  • Publication number: 20220223554
    Abstract: A semiconductor device comprises a substrate body with a surface, a conductor comprising a conductor material covering at least part of the surface, and a dielectric that is arranged on a part of the surface that is not covered by the conductor. Therein, the conductor is in contact with the substrate body, the conductor and the dielectric form a layer, and a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body. Moreover, the semiconductor device is free of a diffusion barrier.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 14, 2022
    Inventors: Jens Hofrichter, Manuel Kaschowitz, Bernhard Poelzl, Karl Rohracher, Amandine Jouve, Viorel Balan, Romain Crochemore, Frank Fournel, Sylvain Maitrejean
  • Publication number: 20210407961
    Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank FOURNEL, Emilie BOURJOT, Séverine CHERAMY, Sylvain MAITREJEAN, Loic SANCHEZ
  • Patent number: 11195711
    Abstract: A method of healing defects generated in a semiconducting layer by implantation of species made in a substrate to form therein an embrittlement plane separating a solid part of the substrate from the semiconducting layer, the semiconducting layer having a front face through which the implanted species pass. The method comprises local annealing of the substrate causing heating of the semiconducting layer, the intensity of which decreases from the front face towards the embrittlement plane. The local annealing may comprise a laser irradiation of a front surface of the substrate.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Pablo Acosta Alba, Frédéric Mazen, Sébastien Kerdiles, Sylvain Maitrejean
  • Patent number: 11081463
    Abstract: A method for directly bonding a first and a second substrate. The method comprises removing surface oxide layers from bonding faces of the first and of the second substrate, and hydrogen passivation of the bonding faces, then, in a vacuum, electron impact hydrogen desorption on the bonding faces followed by placement of the bonding faces in intimate contact with one another.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 3, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Frank Fournel, Vincent Larrey, Sylvain Maitrejean, Christophe Morales
  • Publication number: 20210210345
    Abstract: A method for forming a layer by cycled epitaxy includes at least one sequence of steps each having a first epitaxial deposition forming a first growth layer portion having a first thickness on a first monocrystalline pattern and a second growth layer portion having a second thickness on a second non-monocrystalline pattern, the second thickness being greater than the first thickness, and a second epitaxial deposition forming a first sacrificial layer portion having a third thickness on the first growth layer portion and a second sacrificial layer portion having a fourth thickness on the second growth layer portion. The first and second growth layer portions have an additional element content, greater than the additional element content present in the first and second sacrificial layer portions. The sequence also includes etching the whole of the third and fourth thicknesses and stopping before having consumed the whole of the first thickness.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 8, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent MAZZOCCHI, Sylvain MAITREJEAN
  • Patent number: 10978594
    Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
  • Publication number: 20210104634
    Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Emmanuel AUGENDRE, Maxime ARGOUD, Sylvain MAITREJEAN, Pierre MORIN, Raluca TIRON
  • Publication number: 20210098265
    Abstract: A method is provided for modifying a strain state of a block of a semiconducting material including steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block.
    Type: Application
    Filed: November 24, 2020
    Publication date: April 1, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain MAITREJEAN, Shay REBOH, Romain WACQUEZ
  • Patent number: 10879083
    Abstract: A method is provided for modifying a strain state of a block of a semiconducting material having a crystalline structure, including steps in the following order: a) forming an amorphous lower region in the block of semiconducting material resting on a substrate amorphous, while maintaining the crystalline structure of an upper region of the block, which is in contact with the lower region; b) performing at least one creep annealing of the block with a suitable duration and temperature so that creep occurs in the lower region and without recrystallizing the material of this lower region; and c) performing at least one recrystallization annealing of the lower region of the block.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 29, 2020
    Assignee: Commissariat á l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Maitrejean, Shay Reboh, Romain Wacquez
  • Publication number: 20200219719
    Abstract: A method of healing defects generated in a semiconducting layer by implantation of species made in a substrate to form therein an embrittlement plane separating a solid part of the substrate from the semiconducting layer, the semiconducting layer having a front face through which the implanted species pass. The method comprises local annealing of the substrate causing heating of the semiconducting layer, the intensity of which decreases from the front face towards the embrittlement plane. The local annealing may comprise a laser irradiation of a front surface of the substrate.
    Type: Application
    Filed: January 2, 2020
    Publication date: July 9, 2020
    Inventors: Pablo Acosta Alba, Frédéric Mazen, Sébastien Kerdiles, Sylvain Maitrejean
  • Publication number: 20200194273
    Abstract: Method for producing a semiconductor substrate, including the implementation of the following steps: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the strained semiconductor region; etching the superficial layer according to a pattern of the etching mask, exposing at least one first lateral edge formed by a first strained semiconductor portion belonging to said part of the strained semiconductor region and which is in contact with the buried dielectric layer; modifying the first strained semiconductor portion into a second portion of material forming a mechanical support element arranged against the strained semiconductor region; removing the etching mask.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Applicant: Commissariat A L 'Energie Atomique et aux Energies Alternatives
    Inventors: Shay REBOH, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
  • Patent number: 10665497
    Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 26, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Emmanuel Augendre, Nicolas Loubet, Sylvain Maitrejean, Pierre Morin
  • Publication number: 20200152597
    Abstract: A method for directly bonding a first and a second substrate. The method comprises removing surface oxide layers from bonding faces of the first and of the second substrate, and hydrogen passivation of the bonding faces, then, in a vacuum, electron impact hydrogen desorption on the bonding faces followed by placement of the bonding faces in intimate contact with one another.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 14, 2020
    Inventors: Frank Fournel, Vincent Larrey, Sylvain Maitrejean, Christophe Morales
  • Patent number: 10600786
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 24, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Patent number: 9853124
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Patent number: 9853130
    Abstract: A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: December 26, 2017
    Assignee: Commissariat á l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Jean-Charles Barbe, Benoit Mathieu, Yves Morand