Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation.

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.

Abstract: A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone configured to induce a compressive strain in the first block and a second semi-conductor block covered with a second strain zone configured to induce a tensile strain in the second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of the strain zones; and recrystallizing the lower region of the first and second blocks while using the upper region of crystalline material as starting zone for a recrystallization front.

Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.

Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s) d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract: A Method for modifying the strain state of a semiconducting structure, comprising steps to: a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on the first semiconducting material and elements based on the second semiconducting material, then b) remove portions of the second semiconducting material from the first structure so as to form empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material, e) perform appropriate thermal annealing so as to make the dielectric material creep or relax, and cause a change in the strain state of elements based on the first semiconducting material in the structure.

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorisation technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphised, before the transistor gate is made.

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract: Method for modifying the strain state of a block of a semiconducting material comprising steps for: making a lower region of a block of semiconducting material resting on a substrate amorphous, while the crystalline structure of an upper region of the block in contact with the lower region is maintained, making a creep annealing with a sufficient thermal budget to enable creep of the lower region without recrystallizing the material of this lower region, making a recrystallization annealing of the lower region.

Abstract: Method for producing a microelectronic device comprising: a) the formation on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone adapted to induce a compressive strain in said first block and a second semi-conductor block covered with a second strain zone adapted to induce a tensile strain in said second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of said strain zones, b) the re-crystallization of said lower region of said first block and of said second block while using said upper region of crystalline material as starting zone for a recrystallization front.

Abstract: A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.

Abstract: A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.