Patents by Inventor Sylvie Wuidart

Sylvie Wuidart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080253200
    Abstract: A method for reading of the state of a non-volatile memory element, comprising adjusting including conditioning the frequency of a first oscillatory to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element.
    Type: Application
    Filed: September 13, 2005
    Publication date: October 16, 2008
    Applicant: StMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Patent number: 7388802
    Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: June 17, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Mathieu Lisart, Nicolas Demange
  • Patent number: 7372965
    Abstract: The invention proposes a method of managing an electronic circuit of the type comprising a memory (EEPROM) for the storage of confidential information, the method comprising masking variations of the electrical current (I) consumed by the electronic circuit, during a fraction of the time only (ti-tj), at least during the portion(s) of time during which an instruction bearing on confidential data is executed, and notably an instruction for reading out from the memory (EEPROM).
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: May 13, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Publication number: 20080046693
    Abstract: A digital processing unit for executing program instructions stored in at least two memories and including at least one first register of temporary storage of the operator of a current instruction to be executed and at least a second register of temporary storage of at least one argument or operand of said current instruction, and a protection circuit for submitting, upstream of the register, the operator to a deciphering function if this operator originates from one of the memories or from an area of these memories, identified from the address provided by a program counter. The present invention also relates to a method for protecting a program for updating an electronic circuit and controlling its execution, including at least one step of ciphering or deciphering of program instruction operators.
    Type: Application
    Filed: February 2, 2007
    Publication date: February 21, 2008
    Applicant: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Patent number: 7290151
    Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: October 30, 2007
    Assignee: STMicroelectronics SA
    Inventor: Sylvie Wuidart
  • Publication number: 20070234149
    Abstract: A method and a circuit for protecting the execution of a calculation by an electronic circuit, conditioning a result of the calculation to states of bits indicative of executions of steps of access in read mode and/or in write mode to storage elements.
    Type: Application
    Filed: February 9, 2007
    Publication date: October 4, 2007
    Applicant: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Patent number: 7178067
    Abstract: An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: February 13, 2007
    Assignee: STMicroelectronics SA
    Inventor: Sylvie Wuidart
  • Publication number: 20070002616
    Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.
    Type: Application
    Filed: June 13, 2006
    Publication date: January 4, 2007
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Sylvie Wuidart, Mathieu Lisart, Nicolas Demange
  • Patent number: 7146509
    Abstract: Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: December 5, 2006
    Assignee: STMicroelectronics SA
    Inventors: Fabrice Marinet, Sylvie Wuidart
  • Publication number: 20060126373
    Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 15, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Luc Wuidart
  • Patent number: 7057941
    Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: June 6, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Luc Wuidart
  • Publication number: 20050238120
    Abstract: A method and a circuit for detecting a binary state supported by an analog symbol, comprising sampling the symbol with a sampling signal based on a frequency having a period shorter than the duration of a symbol, selecting a number of significant samples smaller than the number of samples which would be obtained with a sampling of the symbol at said frequency, and deciding of the symbol state based on the selected samples.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 27, 2005
    Inventors: Yveline Guilloux, Romain Palmade, Fabrice Romain, Sylvie Wuidart
  • Patent number: 6937049
    Abstract: A method for testing in parallel several identical integrated circuit chips with an asynchronous operation, via two physical contacts between a tester and each of the chips, including transmitting on the tester side a first test control signal for the integrated circuit chips, having the test executed in desynchronized fashion by each of the integrated circuit chips, transmitting on the tester side, after a predetermined time interval following the transmission of the first control signal, a second result request control signal to the integrated circuit chips, and having all chips respond synchronously upon reception of said second control signal.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 30, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Claude Zahra
  • Patent number: 6927580
    Abstract: A method and a circuit for detecting variations of at least one environmental parameter of an integrated circuit, including evaluating a propagation delay of an edge in delay elements sensitive to variations of the environmental parameter, and comparing the present or measured delay with at least one reference value.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 9, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Luc Wuidart, Michel Bardouillet, Pierre Balthazar
  • Patent number: 6925569
    Abstract: A secured microprocessor includes a rights allocation system for the allocation, to programs executable by the microprocessor, of permanent access rights to certain zones of the memory array of the microprocessor. The rights allocation system confers, on a sub-program shared by at least two programs, temporary rights of access to certain memory zones. The temporary rights are allocated when the sub-program is called by one of the programs as a function of the program calling the sub-program. The rights allocation system provides libraries in a secured microprocessor without harming the integrity of the rights conferred on programs using the libraries.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: August 2, 2005
    Assignee: STMicroelectronics SA
    Inventor: Sylvie Wuidart
  • Publication number: 20040193978
    Abstract: A method for testing in parallel several identical integrated circuit chips with an asynchronous operation, via two physical contacts between a tester and each of the chips, including transmitting on the tester side a first test control signal for the integrated circuit chips, having the test executed in desynchronized fashion by each of the integrated circuit chips, transmitting on the tester side, after a predetermined time interval following the transmission of the first control signal, a second result request control signal to the integrated circuit chips, and having all chips respond synchronously upon reception of said second control signal.
    Type: Application
    Filed: January 28, 2004
    Publication date: September 30, 2004
    Inventors: Sylvie Wuidart, Claude Zahra
  • Publication number: 20040136238
    Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 15, 2004
    Applicant: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Luc Wuidart
  • Publication number: 20040028234
    Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.
    Type: Application
    Filed: June 25, 2003
    Publication date: February 12, 2004
    Applicant: STMicroelectronics SA
    Inventor: Sylvie Wuidart
  • Publication number: 20030219126
    Abstract: A method for scrambling current consumption of an integrated circuit, at least during execution of a confidential operation by the integrated circuit that includes reading confidential data stored therein and/or the calculation of an encryption code is provided. The charge pump is activated to generate current consumption fluctuations on the electrical power supply line of the integrated circuit, at an intensity great enough to mask the current consumption variations associated with the execution of the confidential operation.
    Type: Application
    Filed: March 12, 2003
    Publication date: November 27, 2003
    Applicant: STMicroelectronics SA
    Inventor: Sylvie Wuidart
  • Publication number: 20030126513
    Abstract: An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.
    Type: Application
    Filed: December 11, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart