Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.

Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.

Abstract: A method for scrambling current consumption of an integrated circuit, at least during execution of a confidential operation by the integrated circuit that includes reading confidential data stored therein and/or the calculation of an encryption code is provided. The charge pump is activated to generate current consumption fluctuations on the electrical power supply line of the integrated circuit, at an intensity great enough to mask the current consumption variations associated with the execution of the confidential operation.

Abstract: An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.

Abstract: A method and a circuit for detecting variations of at least one environmental parameter of an integrated circuit, including evaluating a propagation delay of an edge in delay elements sensitive to variations of the environmental parameter, and comparing the present or measured delay with at least one reference value.

Abstract: Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.

Abstract: A secured microprocessor includes a rights allocation system for the allocation, to programs executable by the microprocessor, of permanent access rights to certain zones of the memory array of the microprocessor. The rights allocation system confers, on a sub-program shared by at least two programs, temporary rights of access to certain memory zones. The temporary rights are allocated when the sub-program is called by one of the programs as a function of the program calling the sub-program. The rights allocation system provides libraries in a secured microprocessor without harming the integrity of the rights conferred on programs using the libraries.

Abstract: An integrated circuit includes a microprocessor driven by an internal clock signal and at least one internal peripheral circuit activated selectively by the microprocessor to perform an operation, wherein said circuit includes a circuit for matching the period of the internal clock signal to the operating time of the activated internal peripheral circuit. The integrated circuit can be used as part of any microcontroller.

Abstract: A method and apparatus for sequencing an integrated circuit which receives an external clock signal consists of the use of an internally generated random clock signal and of the use of either of these clock signals depending on the instruction to be performed.

Abstract: Disclosed is a method and apparatus to increase the security of an integrated circuit, the integrated circuit including at least one microprocessor, one or more security sensors to detect abnormal conditions of operation, and registers accessible by the microprocessor which store a state of a respective sensor. The microprocessor reads the contents of a register only at the end of a random period where the duration of the random period is determined by a number generated by a random number generator.

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: A method for detecting the presence of a passivation layer on an integrated circuit comprises sending out a train of pulses of different widths at one end of a line of metal that winds on the surface of the integrated circuit beneath the protection layer of the integrated circuit. The line of metal and the dielectric layer of the integrated circuit form an RC filter. The number of pulses received at the other end of the line of metal is counted and compared with at least one characteristic reference value of the filter.

Abstract: The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: The present invention concerns a method for protecting a write operation of a memory cell within an integrated circuit that comprises the introduction of a random period (d1) between the reception of an external write command and the application of a physical variable to the memory cell so as to thwart the determination of the applied waveform characteristics as a function of time of this physical variable. The present invention also concerns an integrated circuit that comprises a memory whose write operation is protected according to this method. An application of the present invention is in the domain of chip carrying cards, i.e. smartcard applications.

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: In an integrated circuit, a detector of information coherency is associated with a circuit for the storage of information. The detector includes a reference circuit that has the same structure as the storage circuit. The reference circuit contains complementary information under normal circumstances. A checking circuit of the detector verifies the complementary nature of the information in the reference circuit and detects disturbing phenomena that cause incoherence in the information contained in the storage circuit.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are fixed by a current generator through current mirrors and are therefore very stable.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.