Patents by Inventor Syun-Ming Jang

Syun-Ming Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synergy Effect of Alloying Materials in Interconnect Structures
    Publication number: 20100059893
    Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 11, 2010
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • WET CLEANING STRIPPING OF ETCH RESIDUE AFTER TRENCH AND VIA OPENING FORMATION IN DUAL DAMASCENE PROCESS
    Publication number: 20100055897
    Abstract: After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 4, 2010
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Li Chou, Syun-Ming Jang, Jyu-Horng Shieh, Chih-Yuan Ting
  • Metal interconnect structure and process for forming same
    Patent number: 7670947
    Abstract: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsang-Jiuh Wu, Syun-Ming Jang, Ming-Chung Liang, Hsin-Yi Tsai
  • Interconnect structures for semiconductor devices
    Patent number: 7655556
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: February 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Synergy effect of alloying materials in interconnect structures
    Patent number: 7642189
    Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 5, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Dual damascene process without an etch stop layer
    Patent number: 7629690
    Abstract: A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: December 8, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsang-Jiuh Wu, Syun-Ming Jang
  • Synergy Effect of Alloying Materials in Interconnect Structures
    Publication number: 20090152722
    Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line comprises an alloying material; and forming an etch stop layer on the copper line.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Contact or via hole structure with enlarged bottom critical dimension
    Patent number: 7511349
    Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 31, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Fang-Cheng Chen, Chao-Cheng Chen, Syun-Ming Jang
  • Selective Formation of Boron-Containing Metal Cap Pre-layer
    Publication number: 20090014877
    Abstract: An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 15, 2009
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Contact structure formed using supercritical cleaning fluid and ALCVD
    Patent number: 7462561
    Abstract: A supercritical fluid such as CO2 cleans an opening formed in a Si-containing dielectric material and removes polymeric and organic residue produced by the etching process used to form the opening. The opening may be a contact, via or other opening and may include a cross-sectional area of less than 0.2 or 0.1 micron square. Atomic layer chemical vapor deposition (ALCVD) is used to form a thin barrier layer within the opening after the supercritical cleaning. A conductive material is formed over the barrier layer to provide a contact structure with improved contact resistance in VLSI devices.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: December 9, 2008
    Inventors: David Lu, Horng-Huei Tseng, Syun-Ming Jang
  • Method for improving a semiconductor device delamination resistance
    Patent number: 7456093
    Abstract: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
    Type: Grant
    Filed: July 3, 2004
    Date of Patent: November 25, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pi-Tsung Chen, Keng-Chu Lin, Hui-Lin Chang, Lih-Ping Li, Tien-I Bao, Yung-Cheng Lu, Syun-Ming Jang
  • Novel approach for reducing copper line resistivity
    Publication number: 20080286965
    Abstract: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Inventors: Hsien-Ming Lee, Minghsing Tsai, Syun-Ming Jang
  • SELF-ALIGNED DIELECTRIC CAP
    Publication number: 20080280449
    Abstract: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huilin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Metal line formation using advaced CMP slurry
    Publication number: 20080265416
    Abstract: An integrated circuit and methods for forming the same are provided. The method includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Inventors: Shen-Nan Lee, Jin-Yiing Song, Syun-Ming Jang
  • Recessed channel field effect transistor (FET) device
    Patent number: 7429769
    Abstract: A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: September 30, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Carlos H. Diaz, Yi-Ming Sheu, Syun-Ming Jang, Hun-Jan Tao, Fu-Liang Yang
  • Interconnect Structures for Semiconductor Devices
    Publication number: 20080233745
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Application
    Filed: April 23, 2007
    Publication date: September 25, 2008
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Damascene structure with high moisture-resistant oxide and method for making the same
    Patent number: 7414315
    Abstract: A semiconductor device includes a substrate, an inter-metal dielectric (IMD) layer over the substrate, and either a nitrogen-containing tetraethoxysilane (TEOS) oxide layer or an oxygen-rich TEOS oxide layer over the IMD layer. The molecular ratio of oxygen in the oxygen-rich TEOS oxide layer is greater than 70%. The IMD layer comprises an extra-low dielectric constant (ELK) layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsang-Jiuh Wu, Syun-Ming Jang
  • Polymeric particle slurry system and method to reduce feature sidewall erosion
    Patent number: 7407601
    Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: August 5, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou
  • Metal interconnect structure and process for forming same
    Publication number: 20080171442
    Abstract: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventors: Tsang-Jiuh Wu, Syun-Ming Jang, Ming-Chung Liang, Hsin-Yl Tsai
  • Method for forming a strained channel in a semiconductor device
    Publication number: 20080124875
    Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Inventors: Ken Liao, Kuo-Hua Pan, Yun-Hsiu Chen, Syun-Ming Jang, Yi-Ching Lin