Patents by Inventor Syun-Ming Jang

Syun-Ming Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for Semiconductor Device Fabrication
    Publication number: 20150364573
    Abstract: A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Ming-Hsi Yeh, Hsin-Yan Lu, Chao-Cheng Chen, Syun-Ming Jang
  • Fin structure and method for forming the same
    Patent number: 9214513
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Hsiung Lin, Carlos H. Diaz, Hui-Cheng Chang, Syun-Ming Jang, Mao-Lin Huang, Chien-Hsun Wang
  • Method of semiconductor integrated circuit fabrication
    Patent number: 9214383
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Jiun Liu, Chien-An Chen, Ya-Lien Lee, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20150270397
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Hsieh-Ying Hao
  • SEMICONDUCTOR DEVICES WITH CORE-SHELL STRUCTURES
    Publication number: 20150263094
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CARLOS H. DIAZ, CHUN-HSIUNG LIN, HUI-CHENG CHANG, SYUN-MING JANG, CHIEN-HSUN WANG, MAO-LIN HUANG
  • SEMICONDUCTOR DEVICE HAVING INTERCONNECT LAYER THAT INCLUDES DIELECTRIC SEGMENTS INTERLEAVED WITH METAL COMPONENTS
    Publication number: 20150235963
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 20, 2015
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Finlike structures and methods of making same
    Patent number: 9111884
    Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Chao-Cheng Chen, Syun-Ming Jang
  • FIN STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20150228721
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 13, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: CHUN-HSIUNG LIN, CARLOS H. DIAZ, HUI-CHENG CHANG, SYUN-MING JANG, MAO-LIN HUANG, CHIEN-HSUN WANG
  • Interconnect Structure for Semiconductor Devices
    Publication number: 20150214159
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Systems and Methods for Integrated Resputtering in a Physical Vapor Deposition Chamber
    Publication number: 20150206724
    Abstract: The present disclosure is directed to a material layer deposition system. The material layer deposition system includes a wafer pedestal configured to support at least one wafer within a confinement shield structure and a target carrier structure positioned above the wafer pedestal at an opposite side of the confinement shield structure. The target carrier structure is configured to support a sputtering target. The material layer deposition system further includes a collimator disposed within the confinement shield structure between the wafer pedestal and the target carrier structure, an electrical power source coupled to the collimator to supply electrical power, and a control system configured to control the electrical power source coupled to the collimator.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Minghsing Tsai, Syun-Ming Jang
  • METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE
    Publication number: 20150187591
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Application
    Filed: February 20, 2015
    Publication date: July 2, 2015
    Inventors: Chia-Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Ming-Hsing Tsai, Syun-Ming Jang
  • Method to Reduce Etch Variation Using Ion Implantation
    Publication number: 20150187927
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Application
    Filed: February 7, 2014
    Publication date: July 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Bottle-neck recess in a semiconductor device
    Patent number: 9054130
    Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo
  • SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING
    Publication number: 20150155365
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Kuan-Ting Liu, Hung-Chin Chung, Hsien-Ming Lee, Weng Chang, Syun-Ming Jang, Wei-Jen Lo
  • Gap filling method for dual damascene process
    Patent number: 9029260
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Interconnect structure for semiconductor devices
    Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Method of forming pattern for semiconductor device
    Patent number: 8962484
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai, Syun-Ming Jang
  • Finlike Structures and Methods of Making Same
    Publication number: 20150024566
    Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 22, 2015
    Inventors: Ming-Hsi Yeh, Chao-Cheng Chen, Syun-Ming Jang
  • Interconnect Structure for Semiconductor Devices
    Publication number: 20150017800
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 15, 2015
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Chemical dispensing system and method
    Patent number: 8932962
    Abstract: A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weibo Yu, Kuo Bin Huang, Chao-Cheng Chen, Syun-Ming Jang