Patents by Inventor Syun-Ming Jang

Syun-Ming Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing strained-silicon semiconductor device
    Patent number: 8255843
    Abstract: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Hsiu Chen, Syun-Ming Jang, Pang-Yen Tsai
  • Approach for reducing copper line resistivity
    Patent number: 8242016
    Abstract: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ming Lee, Minghsing Tsai, Syun-Ming Jang
  • ANCHORED DAMASCENE STRUCTURES
    Publication number: 20120142188
    Abstract: An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps
    Type: Application
    Filed: March 2, 2011
    Publication date: June 7, 2012
    Inventors: David Lu, Horng-Huei Tseng, Syun-Ming Jang
  • Interconnect Structure for Semiconductor Devices
    Publication number: 20120049371
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Interconnect structure for semiconductor devices
    Patent number: 8053356
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
    Patent number: 8053359
    Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-I Bao, Syun-Ming Jang
  • Selective formation of boron-containing metal cap pre-layer
    Patent number: 7977791
    Abstract: An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: July 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Wet cleaning stripping of etch residue after trench and via opening formation in dual damascene process
    Patent number: 7968506
    Abstract: After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Li Chou, Syun-Ming Jang, Jyu-Horng Shieh, Chih-Yuan Ting
  • METHOD FOR FORMING HIGH-K METAL GATE DEVICE
    Publication number: 20110108928
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Applicant: TAIWAN SEMCONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Wee Tao, Han-Guan Chew, Harry Hak-Lay Chuang, Syun-Ming Jang
  • BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20110049567
    Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.
    Type: Application
    Filed: July 22, 2010
    Publication date: March 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo
  • Interconnect Structure for Semiconductor Devices
    Publication number: 20110027991
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Method of manufacturing strained-silicon semiconductor device
    Publication number: 20110008951
    Abstract: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.
    Type: Application
    Filed: August 27, 2010
    Publication date: January 13, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Hsiu Chen, Syun-Ming Jang, Pang-Yen Tsai
  • Self-aligned dielectric cap
    Patent number: 7863196
    Abstract: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: January 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hulin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Composite Underfill and Semiconductor Package
    Publication number: 20100295173
    Abstract: Embodiments of the invention exploit physical properties of nanostructures by using nanostructures in a composite underfill. An embodiment is a composite underfill comprising an epoxy matrix applied between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy matrix. Another embodiment is a semiconductor package comprising a semiconductor chip, a carrier, wherein the semiconductor chip is bonded to the carrier, and a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip. Further embodiments include a method for creating a semiconductor package comprising a composite underfill.
    Type: Application
    Filed: February 26, 2010
    Publication date: November 25, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Chih-Lung Lin, Syun-Ming Jang
  • Interconnect structure for semiconductor devices
    Patent number: 7834458
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Semiconductor Device Having a Second Level of Metallization Formed over a First Level with Minimal Damage to the First Level and Method
    Publication number: 20100203722
    Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.
    Type: Application
    Filed: April 22, 2010
    Publication date: August 12, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-I BAO, Syun-Ming JANG
  • Method for forming a strained channel in a semiconductor device
    Patent number: 7754571
    Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 13, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken Liao, Kuo-Hua Pan, Yun-Hsiu Chen, Syun-Ming Jang, Yi-Ching Lin
  • Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
    Patent number: 7732326
    Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: June 8, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-I Bao, Syun-Ming Jang
  • Metal Line Formation Through Silicon/Germanium Soaking
    Publication number: 20100090342
    Abstract: A method for forming interconnect structure includes providing a substrate; forming a low-k dielectric layer over the substrate; forming an opening in the low-k dielectric layer; after the step of forming the opening, performing a silicon/germanium soaking process to exposed surfaces of the low-k dielectric layer; and after the silicon/germanium soaking process, filling the opening.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Inventors: Hui-Lin Chang, Chih-Lung Lin, Syun-Ming Jang
  • Interconnect Structure for Semiconductor Devices
    Publication number: 20100090343
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Application
    Filed: December 15, 2009
    Publication date: April 15, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang