Abstract: An IC device includes first and second resistors. The first resistor includes first and second metal segments extending in a first direction in a first metal layer, and a third metal segment extending in a second direction in a second metal layer, and electrically connecting the first and second metal segments. The second resistor includes fourth and fifth metal segments extending in the first direction in the first metal layer, and a sixth metal segment extending in the second direction in a third metal layer, and electrically connecting the fourth and fifth metal segments. The fourth and fifth metal segment have a width greater than a width of the first and second metal segments, the fourth metal segment is between the first and second metal segments and separated from the first metal segment by a distance, and a fourth and fifth metal segment separation is greater than the distance.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: Disclosed herein are related to a device and a method for sensing a temperature. In one aspect, the device includes a first resistor including a first metal rail in a first layer. The first metal rail may have a first thermal-resistance coefficient. In one aspect, the device includes a second resistor including a second metal rail in a second layer above the first layer along a direction. The second metal rail may have a second thermal-resistance coefficient. In one aspect, the device includes a sensing circuit coupled to the first resistor and the second resistor. The sensing circuit may be configured to determine a temperature, according to the first metal rail having the first thermal-resistance coefficient and the second metal rail having the second thermal-resistance coefficient.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A device including a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series. Each of the first plurality of metal-oxide semiconductor field-effect transistors includes a first gate structure, a first drain/source region on one side of the first gate structure, and a second drain/source region on another side of the first gate structure. The first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.

Abstract: A system for designing a temperature sensor arrangement includes a processor and a non-transitory computer readable medium, including instructions, connected to the processor. The processor is configured to execute the instructions for designing a sensor array, the sensor array includes a first transistor of a first device, and a plurality of second transistors of a second device. The processor is configured to execute the instructions for designing a guard ring region between the sensor array and another circuit of an integrated circuit, the guard ring region includes a transistor structure. The processor is configured to execute the instructions for designing a thermally conductive element between the sensor array and the guard ring region, the thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors. The processor is configured to execute the instructions for generating the temperature sensor arrangement.

Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: A method (of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails) includes: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.

Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: A thermal sensor circuit that includes a temperature sensing circuit, an analog to digital converter, a processor and a divider circuit. The temperature sensing circuit generates a first temperature-dependent voltage and a second temperature-dependent voltage. The analog to digital converter converts a voltage difference between the first temperature-dependent voltage and the second temperature-dependent voltage to generate a first bit stream. The processor generates a second bit stream based on a thermal coefficient, wherein the thermal coefficient is used to calibrate the thermal sensor circuit. The processor further tunes the thermal coefficient until the output bit stream is equivalent to a bit stream of a reference model. The divider circuit divides the first bit stream by a denominator value to generate an output bit stream, wherein the denominator value is determined according to a bit value of the second bit stream.

Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A thermal sensor circuit that includes a temperature sensing circuit, an analog to digital converter, a processor, a divider circuit and a digital circuit is introduced. The temperature sensing circuit generates first and second temperature-dependent voltages. The digital to analog converter converts the first and second temperature-dependent voltages to first and second bit streams. The processor generates a third bit stream based on a thermal coefficient. The divider circuit divides one of the first and second bit streams by a denominator value to generate a fourth bit stream, wherein the denominator value is determined according to a bit value of the third bit stream. The digital circuit subtracts the other one of the first and second bit streams from the fourth bit stream to generate an output bit stream. The processor tunes the thermal coefficient until the output bit stream is equivalent to a bit stream of a reference model.

Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, a first switch, and a second switch. The first differential input pair receives an output voltage at an output node and a first temperature-dependent voltage. The second differential input pair receives the output voltage and a second temperature-dependent voltage. When the output voltage reaches the second temperature-dependent voltage, the first switch is turned on to pull up the output voltage in response to a first control signal generated according to an output signal of the second differential input pair. When the output voltage reaches the first temperature-dependent voltage, the second switch is turned on to pull down the output voltage in response to a second control signal generated according to an output signal of the first differential input pair.