Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: An integrated circuit includes a first conducting line and a second conducting line in a first metal layer above a first transistor and a second transistor. The first conducting line and the second conducting line, which are parallel and adjacent to each other, form a metal-insulator-metal capacitor. Each of the first transistor and the second transistor forms a metal-insulator-semiconductor capacitor. The circuit also includes a third conducting line connected to a source and a drain of the first transistor and configured to receive a first reference voltage. The circuit still includes a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: An integrated circuit includes a first temperature-sensitive device configured to generate a first voltage, a second temperature-sensitive device configured to generate a second voltage, and an output terminal configured to generate a reference voltage which is a summation of the first voltage and the second voltage. The first voltage monotonically increases with an absolute temperature. The second voltage monotonically decreases with the absolute temperature. In the integrated circuit, a low-dropout regulator has a first input connected to the output terminal and an output connected to the gate of a power regulating transistor. The channel of the power regulating transistor is connected between a first terminal configured to receive a first supply voltage and a second terminal configured to generate a second supply voltage.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: An IC device includes a heat transfer structure electrically isolated from a resistor. The resistor includes first and second metal segments extending in a first direction in a first metal layer and a third metal segment extending perpendicular to the first direction in a second metal layer below the first metal layer, the third metal segment electrically connecting the first and second metal segments to each other. The heat transfer structure includes fourth and fifth metal segments extending in the first direction in the first metal layer adjacent to the first and second metal segments, sixth and seventh metal segments extending in the second direction in the second metal layer, each of the sixth and seventh metal segments electrically connecting the fourth and fifth metal segments to each other, and a thermally conductive path extending from the sixth or seventh metal segment to an underlying active area.

Abstract: A semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. The one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. The thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. The conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. The conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. The conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: An IC device includes first and second resistors. The first resistor includes first and second metal segments extending in a first direction in a first metal layer, and a third metal segment extending in a second direction in a second metal layer, and electrically connecting the first and second metal segments. The second resistor includes fourth and fifth metal segments extending in the first direction in the first metal layer, and a sixth metal segment extending in the second direction in a third metal layer, and electrically connecting the fourth and fifth metal segments. The fourth and fifth metal segment have a width greater than a width of the first and second metal segments, the fourth metal segment is between the first and second metal segments and separated from the first metal segment by a distance, and a fourth and fifth metal segment separation is greater than the distance.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: Disclosed herein are related to a device and a method for sensing a temperature. In one aspect, the device includes a first resistor including a first metal rail in a first layer. The first metal rail may have a first thermal-resistance coefficient. In one aspect, the device includes a second resistor including a second metal rail in a second layer above the first layer along a direction. The second metal rail may have a second thermal-resistance coefficient. In one aspect, the device includes a sensing circuit coupled to the first resistor and the second resistor. The sensing circuit may be configured to determine a temperature, according to the first metal rail having the first thermal-resistance coefficient and the second metal rail having the second thermal-resistance coefficient.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A device including a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series. Each of the first plurality of metal-oxide semiconductor field-effect transistors includes a first gate structure, a first drain/source region on one side of the first gate structure, and a second drain/source region on another side of the first gate structure. The first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.

Abstract: A system for designing a temperature sensor arrangement includes a processor and a non-transitory computer readable medium, including instructions, connected to the processor. The processor is configured to execute the instructions for designing a sensor array, the sensor array includes a first transistor of a first device, and a plurality of second transistors of a second device. The processor is configured to execute the instructions for designing a guard ring region between the sensor array and another circuit of an integrated circuit, the guard ring region includes a transistor structure. The processor is configured to execute the instructions for designing a thermally conductive element between the sensor array and the guard ring region, the thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors. The processor is configured to execute the instructions for generating the temperature sensor arrangement.

Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.