Abstract: Methods, systems and computer program products for detecting flow-level network traffic anomalies via abstraction levels. An exemplary embodiment includes a method for detecting flow-level network traffic anomalies in a computer network, the method including obtaining current distributions of flow level traffic features within the computer network, computing distances of the current distributions' components from a distributions model, comparing the distances of the current distributions to distance baselines from the distributions model, determining if the distances are above a pre-determined thresholds and in response to one or more of the distances being above the pre-determined thresholds in one or more distributions, identifying the current condition to be abnormal and providing indications to its nature.

Abstract: The present invention provides a method for preparing a silicon substrate and a silicon substrate having a silicon surface comprising a pattern of covalently bound monolayers. Each of the monolayers comprises an alkyne, wherein at least a portion of each monolayer is no more than about 5 molecules of the alkyne wide.

Abstract: The present invention provides a system and method for time-series with compression accuracy as a function of time. Briefly described, in architecture, one embodiment of the system, among others, can be implemented as follows. The system includes a computer with a processor. The system performs a method receiving a data set on the computer, utilizing a plurality of filter banks to transform the data set into a plurality coefficients, wherein each coefficient is associated with a basis function, and quantizing the plurality of coefficients, wherein the quantization maps the plurality of coefficients into certain value ranges. Then, system further performs determining a threshold based upon each coefficient effect on a time domain, disregarding the coefficient that fall below the threshold, and storing any remaining coefficients as compressed data for the data set.

Abstract: A system and method is provided for updating a hash tree in a protected environment. An integrity protection controller is provided for observing one or more system parameters of a storage system and one or more hash tree parameters of the hash trees, and for updating a hash tree in dependence on the storage system parameter and the hash tree parameter.

Abstract: The invention provides methods, apparatus and systems for detecting distributed denial of service (DDoS) attacks within the Internet by sampling packets at a point or points in Internet backbone connections to determine a packet metric parameter. The packet metric parameter which might comprise the volume of packets received is analysed over selected time intervals with respect to specified geographical locations in which the hosts transmitting the packets are located. The expected behaviour can be employed to identify traffic distortions revealing a DDoS attack. In a complementary aspect, the invention provides a method of authenticating packets at routers in order to elevate the QoS of authenticated packets. This method can be used to block or filter packets and can be used in conjunction with the DDoS attack detection system to defend against DDoS attacks within the Internet in a distributed manner.

Abstract: Techniques for encryption and authentication of data. One or more plaintext data blocks ciphertext data blocks and corresponding authentication tags are generated by means of authenticated encryption. A tag tree is generated by means of the authentication tags. The ciphertext data blocks and the tag tree data of the tag tree are stored in an untrusted storage, and the root tag of the tag tree is stored in a trusted storage.

Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.

Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.

Abstract: Disclosed are amino acid prodrugs of compounds of the formula I and pharmaceutically acceptable salts thereof, wherein W, R1, R2, R7, R8, R9 and R10 are as defined in the specification. Such compounds are MEK inhibitors and useful in the treatment of hyperproliferative diseases, such as cancer and inflammation, in mammals. Also disclosed is a method of using such compounds in the treatment of hyperproliferative disease in mammals, and pharmaceutical compositions containing such compounds.

Abstract: The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than the components of the memory array region. The methods can include laterally recessing nitride-containing masking structures associated with the peripheral region to a greater extent than nitride-containing masking structures associated with the memory array region, followed by thermal oxidation of the substrate to form dielectric material adjacent the masking structures.

Abstract: The present invention provides a method for preparing a silicon substrate and a silicon substrate having a silicon surface comprising a pattern of covalently bound monolayers. Each of the monolayers comprises an alkyne, wherein at least a portion of each monolayer is no more than about 5 molecules of the alkyne wide.

Abstract: A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources.

Abstract: Disclosed are compounds of the formula I and pharmaceutically acceptable salts and prodrugs thereof, wherein W, t, R1, R2, R7, R9, R10, R11 and R12 are as defined in the specification. Such compounds are MEK inhibitors and useful in the treatment of hyperproliferative diseases, such as cancer and inflammation, in mammals. Also disclosed is a method of using such compounds in the treatment of hyperproliferative diseases in mammals, and pharmaceutical compositions containing such compounds.

Abstract: A method for implementing bump mapping is provided that is fast enough to be used with real time interactive graphics products. Computationally expensive color values are precalculated for a sample of normal vector orientations as a function of orientation-dependent color variables, collected in a color map, and referenced through the color variables. The color variables are linearly related to angle coordinates that specify the normal vector orientations in a selected coordinate system. Angle coordinates are determined for the vertices of the polygons representing the object to be imaged. During rendering, the vertex angle coordinates are interpolated to provide pixel angle coordinates. Modified angle coordinates are generated by combining the angle coordinates with angle perturbations provided by a perturbation source, and converted to color variables. Color values referenced by the color variables are assigned to the corresponding pixels.

Abstract: Disclosed are methods of treating inflammatory diseases and disorders, such as arthritis and inflammatory bowel disease, in mammals.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: Disclosed are compounds of the Formula I and pharmaceutically acceptable salts and prodrugs thereof, wherein R1, R2, R7, R8 and R9, W, X, Y and Z are as defined in the specification. Such compounds are MEK inhibitors and are useful in the treatment of hyperproliferative diseases, such as cancer and inflammation, in mammals, and inflammatory conditions. Also disclosed are methods of using such compounds in the treatment of hyperproliferative diseases in mammals and pharmaceutical compositions containing such compounds.

Abstract: Disclosed are compounds of the Formula I and pharmaceutically acceptable salts and prodrugs thereof, wherein W, R1, R2, R7, R8, R9 and R10 are as defined in the specification. Such compounds are MEK inhibitors and useful in the treatment of hyperproliferative diseases, such as cancer and inflammation, in mammals. Also disclosed is a method of using such compounds in the treatment of hyperproliferative diseases in mammals, and pharmaceutical compositions containing such compounds.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.