Abstract: For a processor-based device capable of network communications, a workload associated with a wireless link to a network may be partitioned into software and hardware implementable portions based on a link communication profile. In response to a different link communication profile, the workload may be re-configured to simultaneously support another wireless link protocol different than that of the configured wireless link.

Abstract: A flash memory cell comprising a series of floating gate devices being connected to one-another through their source electrodes, which are self-aligned to their respective gate electrodes, where a local tungsten interconnect makes a substantially continuous connection to the self-aligned sources. The flash memory cell is formed by forming floating gate devices having their source electrodes connected together by a conductively doped active area, forming a nitride barrier layer overlying each transistor gate, forming a planarized insulation layer over the nitride barrier layer, removing portions of the planarized insulation layer while using the nitride barrier layer to self-align an interconnect via to the source electrodes, forming a tungsten-based interconnect into the interconnect via, the tungsten-based interconnect running a major length of the source electrodes being connected together and making contact therebetween, and forming a tungsten-based drain plug for each floating gate device.

Abstract: A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device comprises the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: Vibration damping apparatus for vibrating environment such as a light emission microscope and an integrated circuit test head includes a rigid member with remotely controlled clamping apparatus attached to spaced portions of the member. The clamping apparatus engage the microscope and the test head for reducing vibrations, and the clamping apparatus can be readily deactivated for moving the microscope or the test head for alignment purposes. Advantageously, two or more rigid members including pneumatic cylinders can be positioned around the device under test while permitting the use of mechanical probes for engaging nodes of an integrated circuit for test purposes.

Abstract: A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources.

Abstract: FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH peripheral circuitry area. At least some of the FLASH peripheral circuitry area spaced trench isolation regions have maximum depths which are greater than first and second maximum depths of trench isolation regions formed within array area.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device includes the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A protective ring apparatus includes a back plate and a riser wall which projects outward from the back plate. The riser wall is located peripheral to a back plate central access channel. A front frame is connected to a top portion of the riser wall, and the front frame defines a front frame access channel which is in registration with the back plate central access channel. A pair of twist links, located along a common link axis, are connected to opposite sides of the front frame. A removable protector plate is connected to the pair of twist links and, prior to its removal, covers and prevents wires in an open electrical box from being cut by a cutting tool used to cut a window in a sheet of drywall to be installed around an electrical box framed by the plaster ring apparatus.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A method for implementing per-pixel shading is provided that is fast enough to be used with real time interactive graphics products. Computationally expensive color values are precalculated for a sample of normal vector orientations as a function of orientation-dependent color values, collected in a color map, and referenced through the color variables. The color variables are linearly related to angle coordinates that specify the normal vector orientations in a selected coordinate system. Angle coordinates are determined for the vertices of the polygons representing the object to be imaged. During rendering, the vertex angle coordinates are interpolated to provide pixel color angles, which are converted to color variables. Color values referenced by the color variables are assigned to the corresponding pixels.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources.

Abstract: A flash memory device comprising an epitaxial silicon floating gate containing conductive ions and overlying a tunnel oxide material; an inner-dielectric material overlying the epitaxial silicon floating gate, a polycide material overlying the inner-dielectric material, the tunnel oxide material, the epitaxial silicon floating gate, the inner-dielectric material and the polycide material forming a transistor gate, and source and drain electrodes on opposing sides of the transistor gate.

Abstract: A flash memory cell comprising a series of floating gate devices being connected to one-another through their source electrodes, which are self-aligned to their respective gate electrodes, where a local tungsten interconnect makes a substantially continuous connection to the self-aligned sources. The flash memory cell is formed by forming floating gate devices having their source electrodes connected together by a conductively doped active area, forming a nitride barrier layer overlying each transistor gate, forming a planarized insulation layer over the nitride barrier layer, removing portions of the planarized insulation layer while using the nitride barrier layer to self-align an interconnect via to the source electrodes, forming a tungsten-based interconnect into the interconnect via, the tungsten-based interconnect running a major length of the source electrodes being connected together and making contact therebetween, and forming a tungsten-based drain plug for each floating gate device.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.