Abstract: A protective ring apparatus includes a back plate and a riser wall which projects outward from the back plate. The riser wall is located peripheral to a back plate central access channel. A front frame is connected to a top portion of the riser wall, and the front frame defines a front frame access channel which is in registration with the back plate central access channel. A pair of twist links, located along a common link axis, are connected to opposite sides of the front frame. A removable protector plate is connected to the pair of twist links and, prior to its removal, covers and prevents wires in an open electrical box from being cut by a cutting tool used to cut a window in a sheet of drywall to be installed around an electrical box framed by the plaster ring apparatus.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.

Abstract: A process of forming isolation structures in semiconductor substrates comprises exposing a selected region of the substrate to an oxidizing ambient held at a first predetermined temperature. As the temperature of the oxidizing ambient is ramped up towards a second predetermined temperature, a relative equilibrium state between oxidation rate and the oxide viscosity is maintained. The process of the present embodiment advantageously is maintained through, the remainder of the equilibrium state oxidation process, so that an isolation layer can be grown without exerting defect-inducing stress over the silicon substrate.

Abstract: A silicon nitride deposition method includes providing a substrate surface. Silicon is predeposited on at least a portion of the surface. After predeposition of the silicon, silicon nitride is deposited. The substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device comprises the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: A method for implementing per-pixel shading is provided that is fast enough to be used with real time interactive graphics products. Computationally expensive color values are precalculated for a sample of normal vector orientations as a function of orientation-dependent color values, collected in a color map, and referenced through the color variables. The color variables are linearly related to angle coordinates that specify the normal vector orientations in a selected coordinate system. Angle coordinates are determined for the vertices of the polygons representing the object to be imaged. During rendering, the vertex angle coordinates are interpolated to provide pixel color angles, which are converted to color variables. Color values referenced by the color variables are assigned to the corresponding pixels.

Abstract: A method for implementing bump mapping is provided that is fast enough to be used with real time interactive graphics products. Computationally expensive color values are precalculated for a sample of normal vector orientations as a function of orientation-dependent color variables, collected in a color map, and referenced through the color variables. The color variables are linearly related to angle coordinates that specify the normal vector orientations in a selected coordinate system. Angle coordinates are determined for the vertices of the polygons representing the object to be imaged. During rendering, the vertex angle coordinates are interpolated to provide pixel angle coordinates. Modified angle coordinates are generated by combining the angle coordinates with angle perturbations provided by a perturbation source, and converted to color variables. Color values referenced by the color variables are assigned to the corresponding pixels.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device comprises the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces resulting in a substantially native oxide free uniform predeposited silicon substrate surface. A silicon nitride layer is then deposited on the predeposited silicon substrate surface after the silicon predeposition.

Abstract: A method for use in forming a memory cell dielectric includes providing a substrate surface of a memory cell including a silicon based electrode surface. Silicon is predeposited on the electrode surface followed by the deposition of a silicon nitride layer. An incubation time for the start of silicon nitride nucleation at the electrode surface is decreased relative to the incubation time for the start of silicon nitride nucleation when silicon nitride is deposited without predeposition of silicon on the electrode surface. Further, the substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces of the substrate surface resulting in a substantially native oxide free uniform predeposited silicon substrate surface. Thereafter, a silicon nitride layer is deposited on the predeposited silicon substrate surface after the silicon predeposition. Further, another silicon nitride deposition method includes providing a silicon based substrate surface. The substrate surface is nitridated in an atmosphere of dimethylhydrazine, and thereafter, a silicon nitride layer is deposited on the nitridated surface. The nitridation of the substrate surface results in a thickness less than three monolayers of silicon nitride.

Abstract: Emission microscopy testing of semiconductor integrated circuits is accomplished from the back side of a packaged die or a wafer but selectively milling the back surface using high speed (e.g., 40,000-60,000 rpm) milling tool having a 150 grit 0.125 inch diameter laterally translated at 3 inches per minute and taking cuts up to approximately 0.00025 inch (6 microns). In milling a packaged die, a trench is first milled in the molding material holding the die in the package and surrounding the die so that the tool can momentarily pause to switch directions off the die face. The die or wafer can be thinned to less than 200 microns for the emission microscopy testing.

Abstract: An emission microscope is mounted on a transportable structure for use on a test floor and encloses or garages an entire automatic test equipment head to facilitate high-speed testing. Test procedures allow development of static/fixed defects over time. A video mask can be developed based on emission sites on known good devices so that only emission from defect sites of bad devices under test are shown.