Patents by Inventor T. Wang

T. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONNECTOR FOR COLLECTION AND DISPENSING OF BREAST MILK OR COLOSTRUM
    Publication number: 20150065996
    Abstract: An adapter for use in a system for collecting colostrum and/or milk from a breast may include: a body having a predominantly cylindrical shape; a first open end of the body for connecting to a funnel device; a second open end of the body for connecting to a source of suction; a side port between the first and second ends for connecting to a fluid collection device; a catchment area at or near the side port; and a blocking member between the side port and the second end, for preventing colostrum from passing beyond the side port and through the second end. The blocking member may include at least one aperture for allowing suction force to be transmitted from the second end to the first end.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 5, 2015
    Inventors: Rush Lloyd Bartlett II, Frank T. Wang, Ryan J.F. Van Wert, Jules P. Sherman
  • Power management of memory circuits by virtual memory simulation
    Patent number: 8972673
    Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • Replacement of a faulty memory cell with a spare cell for a memory circuit
    Patent number: 8971094
    Abstract: A memory interface device has an address input(s) configured to receive address information from an address stream of a host controller; an address output(s) configured to drive address information, and is coupled to a plurality of memory devices; an address match table comprising at least a revised address corresponding to a spare memory location; a control module configured to determine address information from an address stream from an address command bus coupled to a host controller during a run time operation; and a multiplexer coupled to the address input and coupled to the address output.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 3, 2015
    Assignee: Inphi Corporation
    Inventor: David T. Wang
  • REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT
    Publication number: 20150049539
    Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 19, 2015
    Inventor: David T. WANG
  • Simulating a memory circuit
    Patent number: 8949519
    Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: February 3, 2015
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • METHOD OF USING NON-VOLATILE MEMORIES FOR ON-DIMM MEMORY ADDRESS LIST STORAGE
    Publication number: 20150016192
    Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.
    Type: Application
    Filed: August 29, 2014
    Publication date: January 15, 2015
    Inventors: Hamid Reza RATEGH, David T. WANG, Lawrence TSE
  • Method of fabricating low-dislocation-density epitaxially-grown films with textured surfaces
    Patent number: 8932403
    Abstract: A method for forming a surface-textured single-crystal film layer by growing the film atop a layer of microparticles on a substrate and subsequently selectively etching away the microparticles to release the surface-textured single-crystal film layer from the substrate. This method is applicable to a very wide variety of substrates and films. In some embodiments, the film is an epitaxial film that has been grown in crystallographic alignment with respect to a crystalline substrate.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sandia Corporation
    Inventors: Qiming Li, George T. Wang
  • Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
    Patent number: 8910090
    Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
  • Replacement of a faulty memory cell with a spare cell for a memory circuit
    Patent number: 8902638
    Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 2, 2014
    Assignee: Inphi Corporation
    Inventor: David T. Wang
  • METHODS AND COMPOSITIONS OF MOLECULAR PROFILING FOR DISEASE DIAGNOSTICS
    Publication number: 20140349864
    Abstract: The present invention relates to compositions, kits, and methods for molecular profiling and cancer diagnostics, including but not limited to gene expression product markers, alternative exon usage markers, and DNA polymorphisms associated with cancer. In particular, the present invention provides molecular profiles associated with thyroid cancer, methods of determining molecular profiles, and methods of analyzing results to provide a diagnosis.
    Type: Application
    Filed: November 21, 2013
    Publication date: November 27, 2014
    Applicant: Veracyte, Inc.
    Inventors: Giulia C. Kennedy, Bonnie H. Anderson, Darya I. Chudova, Eric T. Wang, Hui Wang, Moraima Pagan, Nusrat Rabbee, Jonathan I. Wilde
  • Method of fabricating vertically aligned group III-V nanowires
    Patent number: 8895337
    Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Power management in semiconductor memory system
    Patent number: 8879348
    Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: November 4, 2014
    Assignee: Inphi Corporation
    Inventor: David T. Wang
  • Memory circuit system and method
    Patent number: 8868829
    Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 21, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Method of using non-volatile memories for on-DIMM memory address list storage
    Patent number: 8861277
    Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Inphi Corporation
    Inventors: Hamid Reza Rategh, David T. Wang, Lawrence Tse
  • METHOD AND SYSTEM FOR TRANSFERRING USER SETTINGS TO ANOTHER USER RECEIVING DEVICE USING A MOBILE USER DEVICE
    Publication number: 20140282807
    Abstract: A system and method for operating a user receiving device includes a first user device that receives first user settings and stores the first user settings therein. The first user device communicates first user settings to a second user receiving device. The second user receiving device operates with the first user settings.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: THE DIRECTV GROUP, INC.
    Inventors: Kuriacose Joseph, Scott D. Casavant, Sean S. Lee, Phillip T. Wang, Christopher Yang, Woei-Shyang Yee, Wesley W. Huie, Gerard V. Talatinian
  • METHOD AND SYSTEM FOR TRANSFERRING USER SETTINGS TO ANOTHER USER RECEIVING DEVICE
    Publication number: 20140282749
    Abstract: A system and method for operating a user receiving device includes a head end associating a first user device with a user account having first user settings. A first user device communicates a device identifier associated with the user receiving device to the head end. The head end communicates the first user settings associated with the user account to the user receiving device. The user receiving device operates with the first user settings.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: THE DIRECTV GROUP, INC.
    Inventors: Kuriacose Joseph, Scott D. Casavant, Sean S. Lee, Phillip T. Wang, Matthew J. Thompson, Brady C. Tsurutani, David N. Schlacht, Johnny Shum
  • METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS
    Publication number: 20140245238
    Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
  • Configurable multirank memory system with interface circuit
    Patent number: 8819356
    Abstract: An interface circuit that is configured to receive a first read command from a memory controller to read first data stored in a first memory circuit and a second read command to read second data that is stored in a second memory circuit, and transmit the first data and the second data to the memory controller across a data bus without a delay on the data bus between the first data and the second data.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, David T. Wang
  • Performing error detection on DRAMs
    Patent number: 8811065
    Abstract: Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • METHODS AND COMPOSITIONS FOR DIAGNOSIS OF THYROID CONDITIONS
    Publication number: 20140228237
    Abstract: The present invention relates to compositions, kits, and methods for molecular profiling and cancer diagnostics, including but not limited to genomic DNA markers associated with cancer. In particular, the present invention provides molecular profiles associated with thyroid cancer, methods of determining molecular profiles, and methods of analyzing results to provide a diagnosis.
    Type: Application
    Filed: January 13, 2014
    Publication date: August 14, 2014
    Applicant: Veracyte, Inc.
    Inventors: Giulia Kennedy, Bonnie H. Anderson, Darya I. Chudova, Eric T. Wang, Hui Wang, Moraima Pagan, Nusrat Rabbee, Jonathan I. Wilde