Abstract: One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Abstract: An interface circuit that emulates a memory circuit having a first organization using a memory circuit having a second organization, wherein the second organization includes a number of banks, a number of rows, a number of columns, and a number of bits per column.

Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Abstract: A method for growing low-dislocation-density material atop a layer of the material with an initially higher dislocation density using a monolayer of spheroidal particles to bend and redirect or directly block vertically propagating threading dislocations, thereby enabling growth and coalescence to form a very-low-dislocation-density surface of the material, and the structures made by this method.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: Methods for analysis and classification of tolerant intersections, and corresponding systems and computer-readable mediums. A method includes receiving an object model having a plurality of elements, the elements corresponding to a plurality of points. The method includes receiving a selection of a first element and a second element of the plurality of elements and receiving a tolerance. The method includes analyzing an intersection between the first element and the second element based on the tolerance. The method includes classifying the intersection between the first element and the second element based on the analysis and storing the classification.

Abstract: The present invention provides apparatus for dispensing ophthalmic lens packages. A plurality of ophthalmic lens packages are loaded into the apparatus and the apparatus determines an identity of each ophthalmic lens package. A housing stores the ophthalmic lens packages and records a location and identity of each of the lens packages and dispenses a particular ophthalmic lens package.

Abstract: One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Abstract: Techniques are presented for assigning a network address to a computing device. In one embodiment, a network device such as a router may be responsible for assigning a network address (e.g., an IP address) to a connected computing device. For example, in IPv6, the network device provides the computing device with a 64-bit prefix that the computing device then uses to generate a 128-bit unique IP address. The network device typically receives this prefix from another server located in the WAN. In case of a communication failure with the WAN, the network device may be unable to attain the correct prefix. Instead of assigning a random prefix that may cause a conflict if the computing device uses the incorrect prefix on the WAN, the network device may assign a different IP address using a different communication protocol—e.g., IPv4. The computing device can then use IPv4 to access both the LAN and the WAN without risking a conflict.

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract: A method and pump that accurately senses air in a fluid delivery line pulses or activates and deactivates the air sensor(s) multiple times during the pumping phase of the fluid delivery cycle and can generate alarms based upon a single indication or a cumulative indication of air in the line. The pump can include multiple air sensors spaced along the delivery line so that the method can use the multiple signals therefrom to distinguish real moving air bubbles from false positives and/or air bubbles adhered to the inner wall of the line.

Abstract: A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

Abstract: The present invention relates to compounds of formula (I) or pharmaceutical acceptable salts or solvates thereof, wherein G1, R2, R3, R4, R5, n, p, q, Ar1, and Ar2 are defined in the description. The present invention relates also to methods of making said compounds, and compositions comprising said compounds which are useful for inhibiting kinases such as IGF-1R.

Abstract: A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.