Patents by Inventor Ta Chen

Ta Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105518
    Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240103732
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.
    Type: Application
    Filed: May 3, 2023
    Publication date: March 28, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Yu-Ta Chen
  • Publication number: 20240103759
    Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.
    Type: Application
    Filed: May 2, 2023
    Publication date: March 28, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Yu-Ta Chen
  • Publication number: 20240102742
    Abstract: A liquid-cooled cooling structure includes a cooling main body having a condensation chamber and an evaporation chamber arranged vertically therein; a separation member arranged between and separating the condensation chamber and the evaporation chamber, and having a first through hole and a second through hole communicating with the condensation chamber and the evaporation chamber, a dimension of the first through hole being greater than that of the second through hole; a longitudinal partition board received in the condensation chamber and arranged between the first through hole and the second through hole and separating the condensation chamber into a first channel and a second channel; cooling fins extended from an outer perimeter of the cooling main body.
    Type: Application
    Filed: September 25, 2022
    Publication date: March 28, 2024
    Inventors: Yen-Chih CHEN, Chi-Fu CHEN, Wei-Ta CHEN, Hung-Hui CHANG
  • Patent number: 11937901
    Abstract: An arteriovenous fistula (AVF) stenosis detection system and method thereof and sensing device are provided. The AVF stenosis detection system includes: a sensing device including a microphone; and a server coupled to the sensing device. The sensing device contacts a first location of a patient body, wherein there is a first distance between the first location and a second location of an AVF of the patient body, and the first location is located on an extended path of an artery or a vein corresponding to the AVF. The sensing device receives a frequency spectrum signal through the microphone and transmits the frequency spectrum signal to the server. The server calculates a stenosis percentage of the AVF corresponding to the frequency spectrum signal through a machine learning module and transmits the stenosis percentage to the sensing device.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: March 26, 2024
    Assignee: Above Care Inc.
    Inventors: Wei-Ta Chen, Yung-Hsin Chen
  • Publication number: 20240081056
    Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yi-Yeh Chuang, Zih-Song Wang, Li-Ta Chen, Shun-Yu Gao
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Patent number: 11895811
    Abstract: A curved electronic device and a method for manufacturing the same are disclosed. The curved electronic device includes a substrate, a component layer, and a modulation layer. The component layer is disposed on the substrate. The component layer is composed of a plurality of electronic components and their connecting wiring arranged on the substrate. The modulation layer is disposed on the component layer, and includes at least one pattern area and at least one blank area that are formed on the component layer. The blank area allows one part of the electronic components to be exposed out of the modulation layer. The modulation layer and the substrate have different heat absorption rates, so that the positions of the substrate corresponding to the blank area and the pattern area have different degrees of softening, so as to prevent the component layer from being damaged in the process of stretching the substrate.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: February 6, 2024
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., INTERFACE OPTOELECTRONICS (WUXI) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Ping-Hsiang Kao, Wen-You Lai, Po-Lun Chen, Chun-Ta Chen, Po-Ching Lin, Ya-Chu Hsu
  • Patent number: 11886296
    Abstract: An apparatus comprises a processing device that is configured to obtain information about driver installations of a given driver on a plurality of computing devices and to obtain information about system failures from the plurality of computing devices. The processing device is further configured to determine a correlation between the driver installations and the system failures and to determine that the given driver is likely to cause a system failure based at least in part on the determined correlation between the driver installations and the system failures. The processing device is further configured to provide an indication that the given driver is likely to cause a system failure to a given computing device. The indication is configured to cause the given computing device to inhibit a presentation of a recommendation to install the given driver to a user of the given computing device.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 30, 2024
    Assignee: Dell Products L.P.
    Inventors: Wei-Ta Chen, Landon Martin Chambers, John Li
  • Publication number: 20240026064
    Abstract: A modified polyurethane carrier substrate is provided. The modified polyurethane carrier substrate is formed from a modified polyurethane. The modified polyurethane includes a soft segment and a hard segment. The soft segment is formed from a polyol. The hard segment is formed from diisocyanate and a chain extender. The chain extender is dianhydride. A common logarithm of a ratio of a storage modulus of the modified polyurethane carrier substrate at ?30° C. to a storage modulus of the modified polyurethane carrier substrate at 150° C. ranges from 0.40 to 1.30.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: CHIH-LUNG LIN, YI-JYUN LOU, CHEN-TA CHEN
  • Patent number: 11861022
    Abstract: The invention relates to a method, a non-transitory computer program product, and an apparatus for encrypting and decrypting physical-address information. The method includes: receiving a first read command requesting of the flash controller for first physical block addresses (PBAs) corresponding to a logical block address (LBA) range from a host side, wherein each first PBA indicates which physical address that user data of a first LBA of the LBA range is physically stored in a flash device; reading the first PBAs corresponding to the LBA range from the flash device; arranging the first PBAs into entries; encrypting content of each entry by using an encryption algorithm with an encryption parameter to obtain an encrypted entry; and delivering the encrypted entries to the host side.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 2, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Ta Chen
  • Publication number: 20230412181
    Abstract: A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a “0” state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.
    Type: Application
    Filed: May 16, 2023
    Publication date: December 21, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chuan-Hung Hsiao, SATYA NARAYANA GANTA, Sung-Han Wen, Kuan-Ta Chen
  • Patent number: 11848646
    Abstract: An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: December 19, 2023
    Assignee: MEDIATEK INC.
    Inventors: Shih-Hsiung Chien, Sung-Han Wen, Kuan-Ta Chen
  • Patent number: 11846729
    Abstract: A virtual reality positioning device including a casing, a plurality of lenses, and a plurality of optical positioning components is provided. The casing has a plurality of holes. The lenses are installed in the holes, respectively, where a field angle of each of the lenses is greater than or equal to 120 degrees and less than or equal to 160 degrees, and the lenses include convex lenses or Fresnel lenses. The optical positioning components are installed in the casing and aligned to the lenses, respectively. In addition, a virtual reality positioning system and manufacturing method of a virtual reality positioning device are provided.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: December 19, 2023
    Assignee: Acer Incorporated
    Inventors: Li Lin, Ker-Wei Lin, Chun-Ta Chen, Chun-Yu Chen, Hao-Ming Chang, Chun-Hsien Chen, Shih-Ting Huang, Hui-Yen Wang
  • Publication number: 20230402277
    Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Patent number: 11827974
    Abstract: A sputtering system is suitable for sputtering a surface to be sputtered having sections. Each section has a projection height. The sputtering system includes a supporting plate, a sputtering array, and a controller. The sputtering array is arranged on the supporting plate. The sputtering array includes sputtering units. Each section corresponds to at least one of the sputtering units. Each sputtering unit has a driving shaft and a target. The target faces the surface to be sputtered. The controller is electrically connected the driving shaft. The driving shaft drives the target to move relative to the surface to be sputtered. The controller controls a distance between each sputtering unit and the corresponding section of the sections in the direction of the projection height to satisfy a given condition.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 28, 2023
    Assignees: Interface Technology (Chengdu) Co., Ltd., Interface Optoelectronics (Shenzhen) Co., Ltd., General Interface Solution Limited
    Inventors: Po-Lun Chen, Chun-Ta Chen, Tsung-Chen Chou, Chin-Yang Wu, Nai-Hau Shiue
  • Publication number: 20230378971
    Abstract: A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.
    Type: Application
    Filed: January 20, 2023
    Publication date: November 23, 2023
    Inventors: Pang-Yen CHIN, Wei-Hsin TSENG, Kuan-Ta CHEN
  • Patent number: 11819315
    Abstract: A human condition detection device comprises a depth image-taking module for taking a depth image of a target area. A millimeter-wave radar module detects breaths or heartbeats in the target area to provide a signal. A thermal image-taking module takes a thermal image of the target area. A processor module determines whether a person is in the target area based on the depth image. The processor module determines whether there is any breath or heartbeat based on the signal if a person is in the target area. The processor module determines whether there is any abnormal vital sign of the person in the target area based on the signal and the thermal image if there is a breath or heartbeat in the target area. The processor module actuates the warning module to provide a warning if there is an abnormal vital sign of the person in the target area.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 21, 2023
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Kuang-Hua Pai, Chih-Liang Chang, Jyun-Hong Lu, Mim-Nan Yeh, Hung-Ta Chen
  • Publication number: 20230361199
    Abstract: Provided is a device with a replacement spacer structure and a method for forming such a structure. The method includes forming an initial spacer structure, wherein the initial spacer structure has an initial etch rate for a selected etchant. The method further includes removing a portion of the initial spacer structure, wherein a remaining portion of the initial spacer structure is not removed. Also, the method includes forming a replacement spacer structure adjacent to the remaining portion of the initial spacer structure to form a combined spacer structure, wherein the combined spacer structure has an intermediate etch rate for the selected etchant that is less than the initial etch rate for a selected etchant. Further, the method includes etching the combined spacer structure with the selected etchant to form a final spacer structure.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ta Chen, Ming-Chang Wen, Kuo-Feng Yu, Chen-Yu Tai, Yun Lee, Poya Chuang, Chun-Ming Yang, Yoh-Rong Liu, Ya-Ting Yang
  • Patent number: D1009865
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 2, 2024
    Assignee: Acer Incorporated
    Inventors: Chun-Yu Chen, Ker-Wei Lin, Chun-Ta Chen