Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.

Abstract: An inductor device includes a first coil and a second coil. The first coil is wound into a plurality of first circles, and the second coil is wound into a plurality of second circles. At least two of the second circles are interlaced with at least two of the first circles on a first side. The at least two of the second circles are disposed adjacent to each other on the first side. At least one of the first circles is only interlaced with at least one of the second circles on a second side. At least another one of the first circles is only interlaced with at least another one of the second circles on the second side.

Abstract: An 8-shaped inductive coil device that includes a first and a second spiral coils and a connection segment structure is provided. The first spiral coil includes first metal segments and crossing connection segments disposed at a first and a second metal layers respectively and includes first connection terminals. The second spiral coil includes second connection terminals. The connection segment structure electrically couples the first and the second connection terminals. The first and the second spiral coils are disposed along an imaginary line passing through a central region of each of ranges surrounded by the first and the second spiral coils. The connection segment structure and the crossing connection segments electrically couple the part of the first metal segments substantially vertical to the imaginary line, and the connection segment structure and the crossing connection segments are disposed substantially on the imaginary line.

Abstract: A transformer structure includes a first inductor and a second inductor. The first inductor has first turns. The second inductor has second turns. The first inductor and the second inductor are disposed in an interlaced manner. Except jump wires, the first and the second inductors are substantially disposed on a first layer. At least one of the first turns is substantially disposed between another first turn and one of the second turns.

Abstract: An inductor device includes a first and a second inductor. First inductor includes plural first wires and a first connection member. Second inductor includes plural second wires and a second connection member. Part of first wires are winded/located at a first area, and part of first wires are winded/located at a second area. First and second areas are located on two opposite sides of inductor device. First connection member connects first wire located at first area and located at second area. Part of second wires are winded/located at first area, and part of second wires are winded/located at second area. One terminal of second connection member connects a terminal of second wire at an inner side of inductor device, and another terminal of second connection member is disposed outside inductor device. First and second inductors are symmetrical with respect to a center line of inductor device.

Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.

Abstract: An asymmetric spiral inductor fabricated in a semiconductor structure includes a spiral coil, a metal segment, and a connection structure. The spiral coil is substantially disposed in a first metal layer and includes a first terminal and a second terminal. The first terminal is disposed at an outermost turn of the spiral coil, and the second terminal is disposed at an innermost turn of the spiral coil. The metal segment is disposed in a second metal layer different from the first metal layer and has a third terminal and a fourth terminal. The connection structure connects the second terminal and the third terminal. The first terminal and the fourth terminal form the two terminals of the asymmetric spiral inductor. The spiral coil is a polygon with N sides (N>4). A portion of the metal segment has a shape substantially identical to a portion of the contour of the polygon.

Abstract: An inductor and an integrated circuit are provided. The inductor includes a first coil, a second coil, and a third coil. The first coil has a first input terminal and a first output terminal, and the first coil is winded in a first direction from the first input terminal to the first output terminal. The second has a second input terminal and a second output terminal, and the second coil is winded in a second direction which is opposite to the first direction from the second input terminal to the second output terminal. The third has a third input terminal and a third output terminal, and the third input terminal is connected to the first input terminal and the second input terminal.

Abstract: An asymmetric spiral inductor fabricated in a semiconductor structure includes a spiral coil, a metal segment, and a connection structure. The spiral coil is substantially disposed in a first metal layer and includes a first terminal and a second terminal. The first terminal is disposed at an outermost turn of the spiral coil, and the second terminal is disposed at an innermost turn of the spiral coil. The metal segment is disposed in a second metal layer different from the first metal layer and has a third terminal and a fourth terminal. The connection structure connects the second terminal and the third terminal. The first terminal and the fourth terminal form the two terminals of the asymmetric spiral inductor. The spiral coil is a polygon with N sides (N>4). A portion of the metal segment has a shape substantially identical to a portion of the contour of the polygon.

Abstract: The present invention discloses an inductor apparatus. Each of a first section of a second and a fourth quadrant loops are bridged to a first section of a former quadrant loop and are bridged to a third section to a second section of a diagonal quadrant loop. Each of a second section of the second and the fourth quadrant loops are coupled to a third section of the diagonal quadrant loop, and to the second section of a former quadrant loop. A first section of a third quadrant loop is coupled to a first section of the fourth quadrant loop, and to a third section of the first quadrant loop. The second section of the third quadrant loop is coupled to a second section of the fourth quadrant loop and to a third section of the third quadrant loop, and to a third section of the first quadrant loop.

Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.

Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first doped well, a second doped well, a mixed doped well, and a gate structure. The first, the second, and the mixed doped wells are disposed in the semiconductor substrate. At least a part of the first doped well and at least a part of the second doped well are located at two opposites sides of the gate structure in a horizontal direction respectively. The mixed doped well are located between the first doped well and the second doped well. The first and the second doped well include a first conductivity type dopant and a second conductivity type dopant respectively. The mixed doped well includes a mixed dopant. A part of the mixed dopant is identical to the first conductivity type dopant, and another part of the mixed dopant is identical to the second conductivity type dopant.

Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.

Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: An integrated stack transformer is provided, wherein the integrated stack transformer includes a first winding, a second winding and a third winding implemented by a first metal layer, and a fourth winding and a fifth winding implemented by a second metal layer. The second winding is positioned between the first winding and the third winding, the fourth winding substantially overlaps the first winding, the fifth winding substantially overlaps the third winding, and a distance between the fifth winding and the fourth winding is less than a distance between the third winding and the first winding. The first winding, the third winding, the fourth winding and the fifth winding form a part of one of a primary inductor and a secondary inductor of the integrated stack transformer, and the second winding is a part of the other of the primary inductor and the secondary inductor.

Abstract: An integrated inductor includes a first coil and a second coil. The first coil has at least one first turn disposed in a first area and at least one second turn disposed in a second area, a number of the at least one first turn is different from a number of the at least one second turn. The second coil has at least one third turn disposed in the first area and at least one fourth turn disposed in the second area, a number of the at least one third turn is different from a number of the at least one fourth turn. The number of the at least one first turn is different from the number of the at least one third turn, and the number of the at least one second turn is different from the number of the at least one fourth turn.