Patents by Inventor Ta-Hsun Yeh

Ta-Hsun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325977
    Abstract: A semiconductor element including first and second windings. The first winding is substantially located in a first metal layer of a semiconductor structure and includes a first outer coil, a first inner coil, and a first bridging structure. The first bridging structure, located in a range substantially enclosed by the first inner coil, connects the first outer coil and the first inner coil. The second winding is substantially located in a second metal layer of a semiconductor structure and includes a second outer coil, a second inner coil, and a second bridging structure. The second bridging structure, located in a range substantially enclosed by the second inner coil, connects the second outer coil and the second inner coil. The first bridging structure is substantially located in the second metal layer, and the second bridging structure is substantially located in the first metal layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 18, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20190148479
    Abstract: An integrated inductor includes a first coil and a second coil. The first coil has at least one first turn disposed in a first area and at least one second turn disposed in a second area, a number of the at least one first turn is different from a number of the at least one second turn. The second coil has at least one third turn disposed in the first area and at least one fourth turn disposed in the second area, a number of the at least one third turn is different from a number of the at least one fourth turn. The number of the at least one first turn is different from the number of the at least one third turn, and the number of the at least one second turn is different from the number of the at least one fourth turn.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 16, 2019
    Inventors: Hsiao-Tsung YEN, Yuh-Sheng JEAN, Ta-Hsun YEH
  • Patent number: 10269733
    Abstract: The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first ground line includes a first pad, a second pad and a first bonding wire that is a bond wire structure connecting the first pad and the second pad. The first signal line includes a third pad, a fourth pad and a second bonding wire that is a bond wire structure connecting the third pad and the fourth pad.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 23, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10262782
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 16, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20190108935
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: HSIAO-TSUNG YEN, CHENG-WEI LUO, YUH-SHENG JEAN, TA-HSUN YEH
  • Publication number: 20190057965
    Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Inventors: Ta-Hsun YEH, Cheng-Wei LUO, Hsiao-Tsung YEN, Yuh-Sheng JEAN
  • Patent number: 10210981
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10186364
    Abstract: An electronic device includes a first planar inductor and a second planar inductor. The first planar inductor includes at least a first ring structure and a second ring structure interconnected electrically for generating a first magnetic field having a first direction and a second magnetic field having a second direction respectively, wherein the first direction is different from the second direction. The second planar inductor includes at least a third ring structure and a fourth ring structure interconnected electrically for generating a third magnetic field having a third direction and a fourth magnetic field having a fourth direction respectively, wherein the third direction is different from the fourth direction. The first ring structure at least partially overlaps the third ring structure to form a first overlap region, and the second ring structure at least partially overlaps the fourth ring structure to form a second overlap region.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 22, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsiao-Tsung Yen, Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20180366254
    Abstract: An asymmetric spiral inductor fabricated in a semiconductor structure includes a spiral coil, a metal segment, and a connection structure. The spiral coil is substantially disposed in a first metal layer and includes a first terminal and a second terminal. The first terminal is disposed at an outermost turn of the spiral coil, and the second terminal is disposed at an innermost turn of the spiral coil. The metal segment is disposed in a second metal layer different from the first metal layer and has a third terminal and a fourth terminal. The connection structure connects the second terminal and the third terminal. The first terminal and the fourth terminal form the two terminals of the asymmetric spiral inductor. The spiral coil is a polygon with N sides (N>4). A portion of the metal segment has a shape substantially identical to a portion of the contour of the polygon.
    Type: Application
    Filed: May 7, 2018
    Publication date: December 20, 2018
    Inventors: HSIAO-TSUNG YEN, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10153078
    Abstract: An integrated inductor structure includes a first spiral coil, a second spiral coil and a connection metal segment. The first spiral coil includes a plurality of metal segments, a bridging segment and first to fourth terminals. The bridging segment connects the metal segments. The second spiral coil has fifth and sixth terminals. The connecting metal segment connects the third and fifth terminals and the fourth and the sixth terminals. The integrated inductor structure uses the first and second terminals as its input and output terminals. The first and third terminals are on a first imaginary line, which passes a central region of a region surrounded by the first spiral coil. The bridging segment and the central region of the region are on a second imaginary line. An included angle between the two imaginary lines is equal to or greater than 45 degrees and equal to or smaller than 90 degrees.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 11, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10147677
    Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10134684
    Abstract: A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned shield structure includes a center structure unit, a first patterned structure unit, and a second patterned structure unit. The center structure unit includes a first sub-center structure unit and a second sub-center structure unit. The second sub-center structure unit and the first sub-center structure unit are symmetrically disposed with respect to a middle of the center structure unit. The first patterned structure unit is disposed on one side of the center structure unit. The second patterned structure unit is disposed on another side of the center structure unit. The second patterned structure unit and the first patterned structure unit are symmetrically disposed with respect to the center structure unit.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: November 20, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20180330872
    Abstract: An inductor device includes a first and a second inductor unit. The first inductor unit includes a first and a second wire. The first wire is winded to form circles. The second wire is winded with the first wire to form circles. The first and/or the second wire are winded in an interlaced manner at a first terminal, a second terminal, a first side, and a second side. The second inductor unit includes a third and a fourth wire. The third wire is winded to form circles. The fourth wire is winded with the third wire to form circles. The third and/or the fourth wire are winded in an interlaced manner at a third terminal, a fourth terminal, a third side, and a fourth side. The first wired is coupled to the fourth wired, and the second wired is coupled to the third wired.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 15, 2018
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO, Yuh-Sheng JEAN, Ta-Hsun YEH
  • Patent number: 10128033
    Abstract: An inductor device includes a conductor and a connector. The conductor includes a first ring-type structure and a second ring-type structure. The second ring-type structure is coupled to the first ring-type structure. The connector is coupled to the first ring-type structure and the second ring-type structure, and is configured to selectively connect the first ring-type structure and the second ring-type structure such that the conductor forms single loop.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 13, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20180323154
    Abstract: An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.
    Type: Application
    Filed: March 20, 2018
    Publication date: November 8, 2018
    Inventors: Hsiao-Tsung YEN, Yuh-Sheng JEAN, Ta-Hsun YEH
  • Patent number: 10115513
    Abstract: An integrated inductor structure includes a guard ring, a patterned ground shield, and an inductor. The guard ring includes an inner ring, an outer ring, and an interlaced structure. The inner ring is disposed in a first metal layer, and includes at least two inner ring openings. The outer ring is disposed in a second metal layer, and includes at least one outer ring opening. The interlaced structure is coupled to one of the at least two inner ring openings and the outer ring opening in an interlaced manner, such that the outer ring opening is enclosed. The patterned ground shield is disposed at an inner side of the inner ring, and coupled to the inner ring and the outer ring. The inductor is formed above the guard ring and the patterned ground shield.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 30, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20180261565
    Abstract: A semiconductor package structure is disclosed. The semiconductor package structure comprises a plurality of layered structures, a plurality of wires, and a first ring structure. The wires are connected to each of the layered structures. The first ring structure is coupled to at least one of the layered structures and positioned between the wires.
    Type: Application
    Filed: January 23, 2018
    Publication date: September 13, 2018
    Inventors: Hsiao-Tsung YEN, Ping-Yuan DENG, Yuh-Sheng JEAN, Ta-Hsun YEH
  • Publication number: 20180254313
    Abstract: A semiconductor element including first and second windings. The first winding is substantially located in a first metal layer of a semiconductor structure and includes a first outer coil, a first inner coil, and a first bridging structure. The first bridging structure, located in a range substantially enclosed by the first inner coil, connects the first outer coil and the first inner coil. The second winding is substantially located in a second metal layer of a semiconductor structure and includes a second outer coil, a second inner coil, and a second bridging structure. The second bridging structure, located in a range substantially enclosed by the second inner coil, connects the second outer coil and the second inner coil. The first bridging structure is substantially located in the second metal layer, and the second bridging structure is substantially located in the first metal layer.
    Type: Application
    Filed: January 11, 2018
    Publication date: September 6, 2018
    Inventors: Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 9997429
    Abstract: The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first semiconductor substrate; a heat source including at least one heat spot, in which the heat source is on/in the semiconductor substrate or being a part of the semiconductor substrate; at least one first heat conduction layer; at least one first heat conduction structure configured to connect the at least one heat spot with the at least one first heat conduction layer; at least one heat sink trench; and at least one second heat conduction structure configured to connect the at least one first heat conduction layer with the at least one heat sink trench, so as to transmit heat from the heat source to the at least one heat sink trench.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 12, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20180151290
    Abstract: An integrated inductor is disclosed herein. The integrated inductor includes a substrate, an insulation layer, and an inductor. The substrate includes a trench. At least a portion of the insulation layer is formed in the trench. The inductor is disposed in the trench, and the inductor is disposed on the insulation layer.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 31, 2018
    Inventors: Hsiao-Tsung YEN, Yuh-Sheng Jean, Ta-Hsun Yeh