Patents by Inventor Ta-Hsun Yeh

Ta-Hsun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070126543
    Abstract: An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via layer pattern, and the redistribution layer pattern are a coil pattern.
    Type: Application
    Filed: October 11, 2006
    Publication date: June 7, 2007
    Inventors: Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20060221541
    Abstract: A capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric. The first electrode structure includes a plurality of first conductive plates vertically disposed and parallel to one another. The second electrode structure includes a plurality of second conductive plates disposed alternately with the first conductive plates. Each first conductive plate includes a plurality of first conductive bars electrically coupled to the first conductive bar stacked thereon with at least a first conductive via. Each second conductive plate includes a plurality of second conductive bars electrically coupled to the second conductive bar stacked thereon with at least a second conductive via.
    Type: Application
    Filed: March 21, 2006
    Publication date: October 5, 2006
    Inventors: Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20060030114
    Abstract: A method for forming a junction varactor and apparatus thereof are disclosed. The method includes: forming at least one deep N-well in a P-type substrate; forming a P-well in the deep N-well; forming at least one n+ region in the P-well; and performing a contact process to couple the n+ region and the deep N-well to an anode, and to couple the P-well to a cathode.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 9, 2006
    Inventors: Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20060006431
    Abstract: A metal oxide semiconductor (MOS) varactor includes a first terminal and a second terminal, and the MOS varactor comprises a substrate; a deep well, formed on the substrate; and a first MOS device, formed on the deep well; wherein a gate of the first MOS device is coupled to the first terminal, and a source and a drain of the first MOS device are coupled to the second terminal.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 12, 2006
    Inventors: Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20050273623
    Abstract: A protection device disposed in a chip includes a decoding circuit for decoding a password and outputting a decoded signal, and a security circuit, coupled to the decoding circuit, for outputting an enable signal according to the decoded signal. The integrated circuit enables desired function of the chip according to the enable signal. Thus, the protection device can prevent the chip from being duplicated.
    Type: Application
    Filed: May 17, 2005
    Publication date: December 8, 2005
    Inventors: Chen-Chih Huang, Ta-Hsun Yeh
  • Patent number: 6940104
    Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: September 6, 2005
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Chao-Cheng Lee, Tay-Her Tsaur
  • Publication number: 20050083620
    Abstract: An ESD protection circuit installed among a plurality of reference nodes includes a clamping device coupled between two reference nodes among the plurality of reference nodes; a stack-coupling device coupled between the clamping device and one of the reference nodes; and at least a resistive device coupled between the stack-coupling device and another one of the reference nodes.
    Type: Application
    Filed: June 18, 2004
    Publication date: April 21, 2005
    Inventors: Yung-Hao Lin, Tay-Her Tsaur, Ta-Hsun Yeh, Chao-Cheng Lee
  • Publication number: 20050083623
    Abstract: An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 21, 2005
    Inventors: Ta-Hsun Yeh, Yung-Hao Lin, Yuh-Sheng Jean
  • Patent number: 6881996
    Abstract: A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: April 19, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Hon Chen, Ssu-Pin Ma, Ta-Hsun Yeh, Yen-Shih Ho, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou
  • Publication number: 20050029566
    Abstract: A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts.
    Type: Application
    Filed: September 7, 2004
    Publication date: February 10, 2005
    Inventors: Chun-Hon Chen, Ssu-Pin Ma, Ta-Hsun Yeh, Yen-Shih Ho, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou
  • Publication number: 20050012156
    Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.
    Type: Application
    Filed: May 13, 2004
    Publication date: January 20, 2005
    Inventors: Ta-Hsun Yeh, Chao-Cheng Lee, Tay-Her Tsaur
  • Publication number: 20050002139
    Abstract: An ESD clamp circuit includes an ESD detecting unit and a discharge circuit with a longitudinal BJT. The longitudinal BJT is formed on a P-type substrate and includes a deep N-well formed on the P-type substrate, a P-well formed on parts of the deep N-well, a N-well formed on the deep N-well surrounding the P-well, a first N+ region formed on parts of the P-well and electrically coupled to a first voltage, a P+ region formed on the P-well surrounding the first N+ region and electrically coupled to a trigger signal, and a second N+ region formed on the N-well and electrically coupled to a second voltage. In the structure of the longitudinal BJT, the leakage current can be decreased, the current gain can be increased, and the dimension of the ESD clamp circuit can be reduced.
    Type: Application
    Filed: June 17, 2004
    Publication date: January 6, 2005
    Inventors: Ta-Hsun Yeh, Chao-Cheng Lee, Tay-Her Tsaur
  • Patent number: 6812088
    Abstract: This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 2, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hon Chen, Ssu-Pin Ma, Ta-Hsun Yeh, Yen-Shih Ho, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou
  • Patent number: 6667217
    Abstract: A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: December 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Heng-Ming Hsu, Jau-Yuann Chung, Yen-Shih Ho, Chun-Hon Chen, Kuo-Reay Peng, Ta-Hsun Yeh, Kong-Beng Thei, Ssu-Pin Ma
  • Patent number: 6472721
    Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: October 29, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ssu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou, Yen-Shih Ho
  • Publication number: 20020019123
    Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
    Type: Application
    Filed: September 27, 2001
    Publication date: February 14, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ssu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou, Yen-Shih Ho
  • Patent number: 6329234
    Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: December 11, 2001
    Assignee: Taiwan Semiconductor Manufactuirng Company
    Inventors: Ssu-Pin Ma, Chun-Hon Chen, Ta-Hsun Yeh, Kuo-Reay Peng, Heng-Ming Hsu, Kong-Beng Thei, Chi-Wu Chou, Yen-Shih Ho
  • Patent number: 6194295
    Abstract: Provided a process for producing a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal by depositing a bilayer-stacked tungsten metal in a same chamber in the manner of not breaking the vacuum therein. Firstly, a layer of amorphous-like tungsten is deposited to increase thermal stability and to prevent diffusion of fluorine atom. Next, a nitridizing treatment is performed thereon to promote further the barrier property and thermal stability of the amorphous-like tungsten. Finally, conventional selective chemical vapor deposited tungsten having low is deposited on the amorphous-like tungsten. Through the deposition of bilayer tungsten according to the process of the invention, thermal stability of conventional selective chemical vapor deposited tungsten can be increased greatly.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: February 27, 2001
    Assignee: National Science Council of Republic of China
    Inventors: Kow-Ming Chang, I-Chung Deng, Ta-Hsun Yeh
  • Patent number: 6162717
    Abstract: A method of forming the gate structure of a MOS device forms a gate structure over a semiconductor substrate and then treats the sidewalls of the gate structure with nitrous oxide plasma so that the silicon and tungsten atoms within the gate structure can react with activated nitrogen in the plasma to form chemical bonds. Hence, a protective layer is formed on the gate sidewalls, thereby increasing thermal stability of the tungsten suicide layer and the polysilicon layer within the gate structure. Thereafter, an oxide material is formed over the protective layer using a rapid thermal oxidation. Next, spacers are formed over the sidewall oxide layer. Finally, subsequent operations necessary for forming a complete MOS device are performed.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: December 19, 2000
    Assignees: ProMOS Technologies, Inc, Mosel Vitelic, Inc., Siemens AG
    Inventor: Ta-Hsun Yeh
  • Patent number: 6133149
    Abstract: A method of forming a thermally stable tungsten silicide layer. The method includes sequentially forming a polysilicon layer and a tungsten silicide layer over a semiconductor substrate. Then, the semiconductor substrate is exposed to nitrogen (N.sub.2) plasma at room temperature so that a nitridation reaction can be initiated, thereby forming a thin tungsten nitride layer over the tungsten silicide layer. Thereafter, a silicon nitride layer is formed over the tungsten nitride layer. Since the thermal stability of a tungsten nitride layer is higher, the probability of re-crystallization in the tungsten silicide layer when the silicon nitride layer is subsequently deposited is reduced. Moreover, tungsten nitride is able to fill the voids and crevices at the grain boundaries of the tungsten silicide layer after the tungsten silicide layer is re-crystallized. Finally, photolithographic and etching operations are carried out to form a gate structure over the semiconductor substrate.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: October 17, 2000
    Assignees: ProMOS Technologies Inc., Mosel Vitelic Inc., Siemens AG
    Inventor: Ta-Hsun Yeh