Abstract: A semiconductor device includes a substrate, a first trough structure and a second trough structure. The first trough structure which is in the substrate includes a first conductive layer, a first doping layer and a first insulation layer, which is placed between the first conductive layer and the first doping layer. The second trough structure which is in the substrate and separated from the first trough structure by a separation part of the substrate includes a second conductive layer and a second insulation layer. A first contact connects the first doping layer, a second contact connects the separation part, and a third contact connects the second conductive layer. The separation part forms a resistor, coupled between the first contact and the second contact, and the substrate, the second insulation layer and the second conductive layer together form a capacitor, coupled between the second contact and the third contact.

Abstract: An electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation source structure is formed in at least one first semiconductor die. The electromagnetic radiation suppression structure is formed in a second semiconductor die, and is used for generating an inverse electromagnetic radiation against the electromagnetic radiation emission of the electromagnetic radiation source structure by sensing the electromagnetic radiation emission of the electromagnetic radiation source structure, to suppress the electromagnetic radiation emission of the electromagnetic radiation source structure from passing through the electromagnetic radiation suppression structure. Another electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation suppression structure is formed in a printed circuit board.

Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.

Abstract: An electronic device includes a first planar inductor and a second planar inductor. The first planar inductor includes at least a first ring structure and a second ring structure interconnected electrically for generating a first magnetic field having a first direction and a second magnetic field having a second direction respectively, wherein the first direction is different from the second direction. The second planar inductor includes at least a third ring structure and a fourth ring structure interconnected electrically for generating a third magnetic field having a third direction and a fourth magnetic field having a fourth direction respectively, wherein the third direction is different from the fourth direction. The first ring structure at least partially overlaps the third ring structure to form a first overlap region, and the second ring structure at least partially overlaps the fourth ring structure to form a second overlap region.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).

Abstract: A device having a variable inductor includes an inductor having an inductance, a first conductor having a first grounding property, and a second conductor having a second grounding property. The device further includes a first single-mesh structure including a first grid. The first grid includes a first conducting wire electrically connected to the first conductor, and a second conducting wire electrically connected to the first conducting wire and the first conductor, wherein the first conducting wire, the second conducting wire and the first conductor are configured to form a first loop corresponding to the inductor for tuning the inductance. The first single-mesh structure further includes a second grid.

Abstract: A signal-transmission-line structure includes a substrate, a through-silicon via (TSV) trench, a conductive substance, at least a conductor wire, and a dielectric layer. The substrate has a first surface and a second surface opposite to each other. The TSV trench is formed in the first surface of the substrate and extends along the first surface. The bottom surface of the TSV trench is located between the first surface and the second surface of the substrate. The TSV trench is filled with the conductive substance to form a transmission line. The conductor wire is located above the transmission line. The dielectric layer is located on the first surface of the substrate, and separates the conductor wire from the transmission line.

Abstract: An integrated transformer includes a primary inductor and a secondary inductor wherein the primary inductor includes a B turns spiral winding formed by a first metal layer and an A turns winding formed by a second metal layer, wherein the A turns winding formed by the second metal layer and the innermost turns of the B turns spiral winding formed by the first metal layer are substantially overlapped; and the secondary inductor includes a C turns winding at least formed by the second metal layer, wherein the C turns winding formed by the second metal layer of the secondary inductor and a portion of the winding formed by the first metal layer of the primary inductor are substantially overlapped, wherein A is not bigger than B, and A is not bigger than C.

Abstract: An integrated stacked transformer includes a primary inductor and a secondary inductor, and the primary inductor includes at least a first turn and a second turn, and is at least formed by a plurality of windings of a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are two adjacent metal layers, and the second turn of the primary inductor is disposed inside the first turn; the secondary inductor includes at least a first turn, and the secondary inductor is at least formed by at least one winding formed by the second metal layer, wherein the first turn of the secondary inductor substantially overlaps the first turn of the primary inductor; wherein the second turn of the primary inductor includes a segment of a parallel connection structure constructed by the first metal layer and the second metal layer.

Abstract: A semiconductor device with an inductor-capacitor (LC) resonant circuit includes a first insulation layer, an inductor component, and a capacitor component. The inductor component includes a coil-conductor segment and two extension-conductor segments. The coil-conductor segment and the extension-conductor segments are located on a same surface of the first insulation layer, and the extension-conductor segments are coupled to two ends of the coil-conductor segment, respectively. The extension-conductor segments are arranged at an interval, and extend outwards relative to the coil-conductor segment. A first region is defined by the extension-conductor segments and the coil-conductor segment, and the capacitor component is arranged corresponding to the first region in an embedded manner on the other surface, opposite to the inductor component, of the first insulation layer.

Abstract: A signal-transmission-line structure includes a substrate, a through-silicon via (TSV) trench, a conductive substance, at least a conductor wire, and a dielectric layer. The substrate has a first surface and a second surface opposite to each other. The TSV trench is formed in the first surface of the substrate and extends along the first surface. The bottom surface of the TSV trench is located between the first surface and the second surface of the substrate. The TSV trench is filled with the conductive substance to form a transmission line. The conductor wire is located above the transmission line. The dielectric layer is located on the first surface of the substrate, and separates the conductor wire from the transmission line.

Abstract: An integrated circuit (IC) includes a packaging body, multiple interface connectors, a functional chip, and an electrostatic discharge (ESD) protection chip. The interface connectors are located on an outer surface of the packaging body. The functional chip has an electronic functional circuit, and the ESD protection chip has an ESD protection circuit. The ESD protection circuit is connected electrically to an interface connector serving as a data exchange path.

Abstract: An integrated stacked transformer includes a primary winding, a secondary winding and a plurality of bridges, wherein the primary winding is formed by a first metal layer and includes a plurality of segments that are not electrically connected to each other; the secondary winding is form by a second metal layer and includes a plurality of segments that are not electrically connected to each other; the plurality of bridges are formed by a third metal layer. A portion of the bridges is connected to the segments of the primary winding respectively to make the segments of the primary winding form a primary inductor; and another portion of the bridges is connected to the segments of the secondary winding respectively to make the segments of the secondary winding form a secondary inductor.

Abstract: A semiconductor device includes a substrate, a first trough structure and a second trough structure. The first trough structure which is in the substrate includes a first conductive layer, a first doping layer and a first insulation layer, which is placed between the first conductive layer and the first doping layer. The second trough structure which is in the substrate and separated from the first trough structure by a separation part of the substrate includes a second conductive layer and a second insulation layer. A first contact connects the first doping layer, a second contact connects the separation part, and a third contact connects the second conductive layer. The separation part forms a resistor, coupled between the first contact and the second contact, and the substrate, the second insulation layer and the second conductive layer together form a capacitor, coupled between the second contact and the third contact.

Abstract: A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating.

Abstract: A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical trench, an inter-layer dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the interlayer dielectric layer to fill up the vertical trench. The metal layer is electrically connected to a power source.

Abstract: The present invention discloses a circuit lifetime measuring device to estimate the rest lifetime of a target circuit, comprising: a reference clock receiving end for receiving a reference clock; a correlation signal generating circuit for providing a correlation signal in which at least some operating settings of the correlation signal generating circuit and the target circuit vary synchronously; a storage circuit for storing an initial relation between the reference clock and the correlation signal; a measuring circuit, coupled to the reference clock receiving end and the correlation signal generating circuit, for measuring a present relation between the reference clock and the correlation signal; and an estimating circuit, coupled to the storage circuit and the measuring circuit, for generating an estimation value according to the initial relation and the present relation, wherein the estimation value indicates the rest lifetime of the target circuit.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).