Patents by Inventor Ta-Hsun Yeh

Ta-Hsun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140284762
    Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Realtek Semiconductor Corp.
    Inventor: Ta-Hsun Yeh
  • Publication number: 20140284761
    Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of through silicon vias (TSVs), and an inductor. The TSVs are formed in the semiconductor substrate and arranged in a specific pattern, and the TSVs are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of TSVs in the semiconductor substrate and arranging the TSVs in a specific pattern; filling the TSVs with a metal material to form a PGS. forming an inductor above the semiconductor substrate.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Realtek Semiconductor Corp.
    Inventor: Ta-Hsun Yeh
  • Publication number: 20140061881
    Abstract: An integrated circuit (IC) includes a packaging body, multiple interface connectors, a functional chip, and an electrostatic discharge (ESD) protection chip. The interface connectors are located on an outer surface of the packaging body. The functional chip has an electronic functional circuit, and the ESD protection chip has an ESD protection circuit. The ESD protection circuit is connected electrically to an interface connector serving as a data exchange path.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 6, 2014
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ta-Hsun Yeh, Tay-Her Tsaur, Chien-Ming Wu
  • Publication number: 20140054801
    Abstract: An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 27, 2014
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Tay-Her Tsaur, Cheng-Cheng Yen
  • Publication number: 20140035049
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device is formed on a substrate and includes a first first-type metal-oxide-semiconductor field effect transistor (MOSFET) and a second first-type MOSFET. The first first-type MOSFET includes a first gate structure, a first source area and a first drain area on the substrate. The second first-type MOSFET includes a second gate structure, a second source area, and a second drain area on the substrate. A first pocket implant process is applied to the first first-type MOSFET via a first photomask, while a second pocket implant process is applied to the second first-type MOSFET via a second photomask. The first and second gate structures are facing different directions.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 6, 2014
    Applicant: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ta-Hsun YEH, Hui-Min HUANG, Yuh-Sheng JEAN
  • Patent number: 8471357
    Abstract: This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: June 25, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yi Huang, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20120223796
    Abstract: A variable inductor includes an inductor element and a first inductance adjusting circuit. The first inductance adjusting circuit includes a first open-loop structure and a first switch element. The first switch element is coupled to the first open-loop structure. When the first switch element is in a conducting state, the first open-loop structure and the first switch element forms a first closed-loop to induce a first magnetic flux which alters a magnetic flux from the inductor element in operation.
    Type: Application
    Filed: February 14, 2012
    Publication date: September 6, 2012
    Inventors: Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 8116063
    Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor structure composed of a first capacitor and a second capacitor. The MOM capacitor structure has a plurality of symmetrical branch sections, which form an interdigitated structure along a plurality of ring contours. The MOM capacitor structure has an optimal geometrical symmetry, and therefore a better capacitance matching effect can be obtained, and the MOM capacitor structure has a higher unit capacitance. In addition, a capacitance value ratio between the first capacitor and the second capacitor can be adjusted according to different requirements in the MOM capacitor structure. Furthermore, the MOM capacitor structure of the present invention does not need additional masks, and the process cost is cheaper. In addition, due to the semiconductor process improvement, a large amount of metal layers can be stacked, and since the distance between the metal layers becomes smaller, the unit capacitance becomes higher.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: February 14, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Han-Chang Kang
  • Patent number: 7986007
    Abstract: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: July 26, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yi Huang, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Patent number: 7936245
    Abstract: A stacked structure of a spiral inductor includes a first metal layer, a second metal layer, a first set of vias, and a second set of vias. The first metal layer includes a first segment, a second segment, and a third segment, wherein the layout direction of the third segment is different from the layout direction of the first and second segments. The second metal layer includes a fourth segment, a fifth segment, and a sixth segment connected to the fifth segment, wherein the layout direction of the sixth segment is different from the layout direction of the fourth and fifth segments. The first set of vias connects the first and fourth segments, and they construct a first shunt winding. The second set of vias connects the second and fifth segments, and they construct a second shunt winding. The third and sixth segments construct a crossover region.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: May 3, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 7859039
    Abstract: A semiconductor capacitor structure includes a first metal layer, a second metal layer, a first set of via plugs, a second set of via plugs, and a dielectric layer. The first metal layer includes a first portion, a plurality of parallel-arranged second portions, a third portion, and a plurality of parallel-arranged fourth portions. The second metal layer includes a fifth section, a plurality of sixth sections, a seventh section, and a plurality of eighth sections. The first set of via plugs electrically connects the plurality of second sections to the plurality of sixth sections. The second set of via plugs electrically connects the plurality of fourth sections to the plurality of eighth sections.
    Type: Grant
    Filed: June 10, 2007
    Date of Patent: December 28, 2010
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ta-Hsun Yeh
  • Publication number: 20100295648
    Abstract: A stacked structure of a spiral inductor includes a first metal layer, a second metal layer, a first set of vias, and a second set of vias. The first metal layer includes a first segment, a second segment, and a third segment, wherein the layout direction of the third segment is different from the layout direction of the first and second segments. The second metal layer includes a fourth segment, a fifth segment, and a sixth segment connected to the fifth segment, wherein the layout direction of the sixth segment is different from the layout direction of the fourth and fifth segments. The first set of vias connects the first and fourth segments, and they construct a first shunt winding. The second set of vias connects the second and fifth segments, and they construct a second shunt winding. The third and sixth segments construct a crossover region.
    Type: Application
    Filed: May 4, 2010
    Publication date: November 25, 2010
    Inventors: Kai-Yi Huang, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 7612645
    Abstract: An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via layer pattern, and the redistribution layer pattern are a coil pattern.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: November 3, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20090146252
    Abstract: This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring.
    Type: Application
    Filed: November 25, 2008
    Publication date: June 11, 2009
    Inventors: Kai-Yi Huang, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20090091875
    Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor structure composed of a first capacitor and a second capacitor. The MOM capacitor structure has a plurality of symmetrical branch sections, which form an interdigitated structure along a plurality of ring contours. The MOM capacitor structure has an optimal geometrical symmetry, and therefore a better capacitance matching effect can be obtained, and the MOM capacitor structure has a higher unit capacitance. In addition, a capacitance value ratio between the first capacitor and the second capacitor can be adjusted according to different requirements in the MOM capacitor structure. Furthermore, the MOM capacitor structure of the present invention does not need additional masks, and the process cost is cheaper. In addition, due to the semiconductor process improvement, a large amount of metal layers can be stacked, and since the distance between the metal layers becomes smaller, the unit capacitance becomes higher.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 9, 2009
    Inventors: Ta-Hsun Yeh, Han-Chang Kang
  • Publication number: 20080251841
    Abstract: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 16, 2008
    Inventors: Kai-Yi Huang, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20080237792
    Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor structure having a plurality of symmetrical ring type sections. The MOM capacitor structure of the present invention does not need photomasks above standard CMOS process, and thus the process cost is cheaper. In addition, due to the semiconductor process improvement, a significantly large number of metal layers can be stacked in the MOM capacitor structure, and since the distance between the metal layers becomes smaller, the unit capacitance will be increased.
    Type: Application
    Filed: March 18, 2008
    Publication date: October 2, 2008
    Inventors: Han-Chang Kang, Ta-Hsun Yeh
  • Patent number: 7327555
    Abstract: A capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric. The first electrode structure includes a plurality of first conductive plates vertically disposed and parallel to one another. The second electrode structure includes a plurality of second conductive plates disposed alternately with the first conductive plates. Each first conductive plate includes a plurality of first conductive bars electrically coupled to the first conductive bar stacked thereon with at least a first conductive via. Each second conductive plate includes a plurality of second conductive bars electrically coupled to the second conductive bar stacked thereon with at least a second conductive via.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: February 5, 2008
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20070291439
    Abstract: A semiconductor capacitor structure includes a first metal layer, a second metal layer, a first set of via plugs, a second set of via plugs, and a dielectric layer. The first metal layer includes a first portion, a plurality of parallel-arranged second portions, a third portion, and a plurality of parallel-arranged fourth portions. The second metal layer includes a fifth section, a plurality of sixth sections, a seventh section, and a plurality of eighth sections. The first set of via plugs electrically connects the plurality of second sections to the plurality of sixth sections. The second set of via plugs electrically connects the plurality of fourth sections to the plurality of eighth sections.
    Type: Application
    Filed: June 10, 2007
    Publication date: December 20, 2007
    Inventor: Ta-Hsun Yeh
  • Patent number: 7245467
    Abstract: An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: July 17, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ta-Hsun Yeh, Yung-Hao Lin, Yuh-Sheng Jean