Abstract: An apparatus comprises a nanowire having a channel region, a gate structure surrounding a lower portion of the channel region, wherein the gate structure comprises a first dielectric layer comprising a vertical portion and a horizontal portion, a first workfunction metal layer over the first dielectric layer comprising a vertical portion and a horizontal portion and a low-resistivity metal layer over the first workfunction metal layer, wherein an edge of the low-resistivity metal layer and an edge of the vertical portion of the first workfunction metal layer are separated by a dielectric region and the low-resistivity metal layer is electrically coupled to the vertical portion of the first workfunction metal layer through the horizontal portion of the first workfunction metal layer.

Abstract: An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer.

Abstract: A device comprises a nanowire over a substrate, wherein the nanowire comprises a first drain/source region over the substrate, a channel region over the first drain/source region and a second drain/source region over the channel region, a high-k dielectric layer and a control gate layer surrounding a lower portion of the channel region and a tunneling layer and a ring-shaped floating gate layer surrounding an upper portion of the channel region.

Abstract: Systems for protecting a circuit from an electrostatic discharge (ESD) voltage are provided. An input terminal receives an input signal. An ESD protection circuit receives the input signal from the input terminal. The ESD protection circuit includes one or more vertical nanowire field effect transistors (FETs). Each of the one or more vertical nanowire FETs includes a well of a first conductivity type. Each of the one or more vertical nanowire FETs also includes a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end. The source region further includes a portion formed in the well, where the source region and the drain region are of a second conductivity type. A gate region surrounds a portion of the nanowire and is separated from the drain region by a distance.

Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Abstract: Systems for protecting a circuit from an electrostatic discharge (ESD) voltage are provided. An input terminal receives an input signal. An ESD protection circuit receives the input signal from the input terminal. The ESD protection circuit includes one or more vertical nanowire field effect transistors (FETs). Each of the one or more vertical nanowire FETs includes a well of a first conductivity type. Each of the one or more vertical nanowire FETs also includes a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end. The source region further includes a portion formed in the well, where the source region and the drain region are of a second conductivity type. A gate region surrounds a portion of the nanowire and is separated from the drain region by a distance.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Abstract: A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

Abstract: An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer.

Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.

Abstract: A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer.

Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.

Abstract: A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.

Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.