Patents by Inventor Ta-Te Chou

Ta-Te Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8865526
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8421214
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: April 16, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8269338
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface. An externally exposed housing encloses the semiconductor die and the first end portion of the lead frame, said housing including a metallic plate facing the second attachment surface of the lead frame.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: September 18, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: 8048714
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: November 1, 2011
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: 7768104
    Abstract: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 3, 2010
    Assignee: Vishay General Semiconductor, Inc.
    Inventors: Ta-Te Chou, Hui-Ying Ding, Yun Zhang, Hong-Yun He, Li-Zhu Hao
  • Patent number: 7719096
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: May 18, 2010
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Publication number: 20090236705
    Abstract: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions.
    Type: Application
    Filed: March 18, 2008
    Publication date: September 24, 2009
    Applicant: VISHAY GENERAL SEMICONDUCTOR, INC.
    Inventors: TA-TE CHOU, HUI-YING DING, YUN ZHANG, HONG-YUN HE, LI-ZHU HAO
  • Publication number: 20090096078
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Applicant: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Publication number: 20080036057
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface. An externally exposed housing encloses the semiconductor die and the first end portion of the lead frame, said housing including a metallic plate facing the second attachment surface of the lead frame.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Applicant: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Publication number: 20080036073
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.
    Type: Application
    Filed: July 9, 2007
    Publication date: February 14, 2008
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Publication number: 20080036072
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.
    Type: Application
    Filed: July 9, 2007
    Publication date: February 14, 2008
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: D573116
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: July 15, 2008
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: D616387
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: May 25, 2010
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: D654881
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 28, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian