Patents by Inventor Tadamasa Toma

Tadamasa Toma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119573
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry corrects a base motion vector using a correction value in a fixed direction; and encodes a current partition by using the corrected base motion vector corrected. The correction value is specified by an index indicating one of correction values included in a table. The table is selected from among a plurality of tables, wherein the correction values in one of the plurality of tables have different increments from the correction values in another one of the plurality of tables.
    Type: Application
    Filed: November 18, 2024
    Publication date: April 10, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Kiyofumi ABE, Tadamasa TOMA, Takahiro NISHI
  • Patent number: 12273555
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: April 8, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 12273591
    Abstract: According to one aspect of the present disclosure, a transmission method for enabling transmission of content using a broadcast and a communication channel includes: transmitting playback control information and service information using at least the broadcast wave, the service information being information for playing back content transmission using the broadcast and content transmission using the communication channel when the content is transmitted using the broadcast and the communication channel. The service information includes the content and location information that indicates a location for acquiring meta-information on playback control of the second content. The playback control information includes indexes of a relationship between the first content data and the second content data.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: April 8, 2025
    Assignee: SUN PATENT TRUST
    Inventors: Tadamasa Toma, Noritaka Iguchi, Takahiro Nishi, Hisaya Katou
  • Patent number: 12273580
    Abstract: A transmitting method according to one aspect of the present disclosure includes transmitting a first stream, the first stream including: timing update identification information id1 indicating whether or not a correspondence relationship between a first reference clock and a second reference clock has been updated, the first reference clock being used to transmit and receive the first stream, and the second reference clock being used to transmit and receive a second stream related to another content to be reproduced in synchronization with the content related to the first stream; a first time according to the first reference clock; and a second time according to the second reference clock, the second time being associated with the first time based on the updated correspondence relationship.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: April 8, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tadamasa Toma, Noritaka Iguchi, Hisaya Katou
  • Patent number: 12273522
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, determines whether a first block is available and whether a second block is available, the first block and the second block being defined relative to a current block to be processed; selects a context model based on whether the first block is available, whether the second block is available, which of inter prediction and intra prediction is to be applied to the first block, and which of inter prediction and intra prediction is to be applied to the second block; and encodes, using the context model selected, a parameter indicating which of intra prediction and inter prediction is to be applied to the current block.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: April 8, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chong Soon Lim, Hai Wei Sun, Jing Ya Li, Han Boon Teo, Ru Ling Liao, Che Wei Kuo, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe
  • Publication number: 20250113051
    Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Ru Ling LIAO, Jing Ya LI, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH
  • Patent number: 12267521
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs a primary transform on a derived prediction error, performs a secondary transform on a result of the primary transform, quantizes a result of the secondary transform, and encodes a result of the quantization as data of an image. When a current block to be processed has a predetermined shape, the encoder performs the secondary transform using, among secondary transform basis candidates that are secondary bases usable in the secondary transform, only a secondary transform basis candidate having a size that is not largest size containable in the current block.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: April 1, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Ryuichi Kanoh, Tadamasa Toma, Kiyofumi Abe, Takahiro Nishi
  • Patent number: 12267499
    Abstract: A decoder includes circuitry and memory. In both of a first type of residual decoding where an inverse orthogonal transform is applied and a second type of residual decoding where the inverse orthogonal transform is skipped, wherein when a restriction on a number of CABAC processes allows CABAC decoding of a set of coefficient information flags, the circuitry: decodes the coefficient information flags by CABAC; and otherwise, the circuitry: skips the CABAC decoding of the coefficient information flags; and the circuitry decodes a remainder value of the coefficient with Golomb-Rice decoding when the coefficient information flags are decoded; and otherwise the circuitry decodes a value of the coefficient with the Golomb-Rice decoding, wherein in the second type of residual decoding, the circuitry decodes absolute value flags each relating to an absolute value of the coefficient after decoding the coefficient information flags and before decoding the remainder value of the coefficient.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 1, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yusuke Kato, Takahiro Nishi, Tadamasa Toma, Kiyofumi Abe
  • Publication number: 20250106417
    Abstract: A decoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: decodes a plurality of sets of neural network information each of which identifies a neural network filter; decodes, from one access unit, two or more sets of activation information each of which specifies one set of neural network information among the plurality of sets of neural network information; and applies, to one picture, two or more neural network filters identified by two or more sets of neural network information specified by the two or more sets of activation information.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Han Boon TEO, Jingying GAO, Chong Soon LIM, Praveen Kumar YADAV, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250106424
    Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Han Boon TEO, Takahiro NISHI, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20250104369
    Abstract: An information processing device constructs, in a virtual space, a three-dimensional (3D) model of a target object to be worked on by a worker in a real space, acquires position information and orientation information of the worker in the real space, synchronizes a position and an orientation of a virtual camera in the virtual space with a position and an orientation of the worker based on the position information and the orientation information, generates a virtual camera video which shows the 3D model captured by the synchronized virtual camera, and outputs output information for displaying an output image that includes the virtual camera video.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Minami NAKA, Satoshi MATSUI, Tadamasa TOMA
  • Publication number: 20250106418
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs prediction on an image. A motion vector predictor list used in the prediction includes a spatially neighboring motion vector predictor obtained from a block spatially neighboring a current block, and a spatially broad motion vector predictor obtained from a block positioned at any of a plurality of predetermined positions in a second range that is broader than a first range that spatially neighbors the current block. The plurality of predetermined positions are defined by a regular interval using the top-left of a current picture as a reference point.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250106440
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Han Boon TEO, Jing Ya LI, Che-Wei KUO, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250106423
    Abstract: An image encoder includes circuitry and a memory, wherein the circuitry, in operation, obtains a current block from a coding tree unit (CTU); determines whether inter prediction is to be applied to the current block; in response to determining that the inter prediction is to be applied, performs a partition prediction process; and, in response to determining that the inter prediction is not to be applied, encodes the current block without using the partition prediction process. The partition prediction process includes predicting first values of a set of pixels between a first partition and a second partition in the current block, using a first motion vector for the first partition; predicting second values of the set of pixels, using a second motion vector for the second partition; weighting the first values and the second values; and generating a prediction image for the current block using the weighted first and second values.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Patent number: 12262010
    Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Chong Soon Lim, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Ru Ling Liao, Takahiro Nishi, Tadamasa Toma
  • Patent number: 12262038
    Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.
    Type: Grant
    Filed: January 22, 2024
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Han Boon Teo, Jing Ya Li, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Patent number: 12262004
    Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Patent number: 12262049
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Patent number: 12262058
    Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 25, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masato Ohkawa, Hideo Saitou, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Publication number: 20250097477
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, and generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry modifies the first coefficient value by performing an arithmetic right shift by 7 bits on the first coefficient value. The circuitry generates a third coefficient value by adding the modified first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO