Patents by Inventor Tadanobu Inoue
Tadanobu Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150234970Abstract: In one embodiment, a source mask optimization (SMO) method is provided that includes controlling bright region efficiency during at least one optical domain step. The bright region efficiency being the proportion of the total transmitted light that is transferred to bright areas of a target pattern. The optical domain intermediate solution provided by the at least one optical domain step may then be binarized to obtain an initial spatial domain solution with a controlled MEEF (Mask Error Enhancement Factor). The MEEF is controlled during at least one spatial domain step that optimizes the initial spatial domain solution.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tadanobu Inoue, David O. Melville, Alan E. Rosenbluth, Masaharu Sakamoto, Kehan Tian
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Publication number: 20150088292Abstract: Acquiring expected precision even in a case that partial shrinkage occurs. The present invention is a technique for providing data for minimizing a difference between dimensions of a three-dimensional structure formed by laser radiation and design values of a scan path of the three-dimensional structure, in which the technique includes: modeling a manufacturing process of the three-dimensional structure and formulating a shrinkage of material used in the manufacturing process; and performing an optimization calculation for minimizing the difference between the dimensions of the three-dimensional structure after the shrinkage of the material and the design values by using the formulated shrinkage model to compute the scan length x minimizing the difference, and in which the formulation includes formulating a shrinkage function in the case where the material shrinks according to the scan length xi of the scan path of the laser.Type: ApplicationFiled: September 19, 2014Publication date: March 26, 2015Inventors: Tadanobu Inoue, Yasunao Katayama, Masaharu Sakamoto
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Patent number: 8959462Abstract: A method, an article of manufacture, and a system for designing a mask. The method for designing a mask is implemented by a computer device having a memory, a processor device communicatively coupled to the memory, and a module configured to carry out the method including the steps of: generating an optical domain representation from a design pattern and an imaging light; and optimizing the optical domain representation under a constraint that values of negative excursions at predetermined evaluation points must be greater than or equal to predetermined negative threshold values assigned to the predetermined evaluation points; where: the optical domain representation is a variable representation of a wavefront; the imaging light is light that is transmitted through the mask; the negative excursions are in an object domain representation of the optical domain representation; and the predetermined evaluation points are in the object domain representation.Type: GrantFiled: March 12, 2013Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O Melville, Alan E Rosenbluth, Masaharu Sakamoto, Kehan Tian
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Patent number: 8954898Abstract: Systems and methods for optimizing a source shape and a mask shape for a lithography process are disclosed. One such method includes performing a mask optimization for the lithography process in accordance with a set of parameters including at least one variable representation, at least one objective and problem constraints. Further, a light source optimization for the lithography process is performed in accordance with the set of parameters. In addition, a joint light source-mask optimization is performed in accordance with the set of parameters. The method further includes iterating at least one of the mask optimization or the light source optimization by changing at least one of the variable representation, the objective or the problem constraints to maximize a common process window for the lithography process.Type: GrantFiled: March 15, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O. Melville, Alan E. Rosenbluth, Masaharu Sakamoto, Kehan Tian
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Patent number: 8906293Abstract: An object of the invention is to provide a magnesium alloy having high strength and sufficient formability. A magnesium alloy mainly contains magnesium and has high tensile strength and high compression strength. The crystal grain structure of the alloy has a high angle grain boundary, and the inside of the crystal grain surrounded by the high angle grain boundary is composed of subgrains.Type: GrantFiled: October 2, 2008Date of Patent: December 9, 2014Assignee: National Institute for Materials ScienceInventors: Toshiji Mukai, Hidetoshi Somekawa, Tadanobu Inoue, Alok Singh
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Patent number: 8876451Abstract: Provided is a high-strength bolt which has a tensile strength of 1,200 MPa or more while exhibiting excellent ductility and delayed facture resistance, and further has an excellent impact toughness which had not been obtained in the conventional high-strength bolt. The high-strength bolt has a tensile strength of 1.2 GPa or more and includes a threaded portion and cylindrical neck portion. The bolt has K of 0.8 or more and satisfies Ho<Hs, where K is defined by the equation: (Ao×Ho)/(As×Hs)=K, in which Ao is an effective cross-sectional area of the cylindrical neck portion with a diameter larger than that of the threaded portion, Ho is a Vickers hardness of a portion at which Ao is measured, As is an effective cross-sectional area of the threaded portion, and Hs is a Vickers hardness of the threaded portion.Type: GrantFiled: September 10, 2010Date of Patent: November 4, 2014Assignees: National Institute for Materials Science, Fusokiko Co., Ltd., Kyowa Kogyosyo Co., Ltd.Inventors: Yuuji Kimura, Tadanobu Inoue, Shuji Murasaki, Mataichi Fukuda
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Patent number: 8719735Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.Type: GrantFiled: July 14, 2011Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Masaharu Sakamoto, Alan E. Rosenbluth, Marc Alan Szeto-Millstone, Tadanobu Inoue, Kehan Tian, Andreas Waechter, Jonathan Lee, David Osmond Melville
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Patent number: 8625161Abstract: Digital halftoning processes for producing a halftone image include, for each pixel in the image: indexing a two-dimensional look up table using a position of the pixel, identifying a threshold value for the pixel from the two-dimensional look up table, creating an index that indexes a three-dimensional lookup table using the threshold value and the position of the pixel, and obtaining an output value for the pixel from the three-dimensional look up table via the index. The digital halftoning processes also produce a halftone representation of the image from output values for corresponding pixels.Type: GrantFiled: November 19, 2009Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Larry Ernst, Tadanobu Inoue, Mikel Stanich, Chai W. Wu
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Publication number: 20130263063Abstract: A method, an article of manufacture, and a system for designing a mask. The method for designing a mask is implemented by a computer device having a memory, a processor device communicatively coupled to the memory, and a module configured to carry out the method including the steps of: generating an optical domain representation from a design pattern and an imaging light; and optimizing the optical domain representation under a constraint that values of negative excursions at predetermined evaluation points must be greater than or equal to predetermined negative threshold values assigned to the predetermined evaluation points; where: the optical domain representation is a variable representation of a wavefront; the imaging light is light that is transmitted through the mask; the negative excursions are in an object domain representation of the optical domain representation; and the predetermined evaluation points are in the object domain representation.Type: ApplicationFiled: March 12, 2013Publication date: October 3, 2013Inventors: Tadanobu Inoue, David O. Melville, Alan E. Rosenbluth, Masaharu Sakamoto, Kehan Tian
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Patent number: 8539390Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the mask, for determining a manufacturing penalty in making the mask. The manufacturability of the mask, including the manufacturing penalty in making the mask, is determined based on the target edge pairs as selected, and is dependent on the manufacturing penalty in making the mask. Determining the manufacturability of the mask includes, for a selected edge pair having first and second edges that are at least substantially parallel to one another, determining a manufacturing shape penalty owing to an aspect ratio of the first edge relative to a size of a gap between the first edge and the second edge. This penalty takes into account a pair of connected edges of the first edge that are at least substantially parallel to the first edge.Type: GrantFiled: January 31, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, Alan E. Rosenbluth, Kehan Tian, David O. Melville, Masaharu Sakamoto
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Patent number: 8453076Abstract: Optical wave data for a semiconductor device design is divided into regions. First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region and not accounting for the wave data of neighboring regions of each region. The optical wave data of each region is normalized based on results of the first wavefront engineering. Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as has been normalized. The second wavefront engineering takes into account the wave data of each region and a guard band around each region that includes the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed by organizing the regions into groups, and sequentially performing the second wavefront engineering on the regions of each group in parallel.Type: GrantFiled: March 16, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O. Melville, Hidemasa Muta, Alan E. Rosenbluth, Kehan Tian, Masaharu Sakamoto, Saeed Bagheri
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Publication number: 20130019211Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Inventors: Masaharu Sakamoto, Alan E. Rosenbluth, Marc Alan Szeto-Millstone, Tadanobu Inoue, Kehan Tian, Andreas Waechter, Jonathan Lee, David Osmond Melville
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Publication number: 20120230800Abstract: Provided is a high-strength bolt which has a tensile strength of 1,200 MPa or more while exhibiting excellent ductility and delayed facture resistance, and further has an excellent impact toughness which had not been obtained in the conventional high-strength bolt. The high-strength bolt has a tensile strength of 1.2 GPa or more and includes a threaded portion and cylindrical neck portion. The bolt has K of 0.8 or more and satisfies Ho<Hs, where K is defined by the equation: (Ao×Ho)/(As×Hs)=K, in which Ao is an effective cross-sectional area of the cylindrical neck portion with a diameter larger than that of the threaded portion, Ho is a Vickers hardness of a portion at which Ao is measured, As is an effective cross-sectional area of the threaded portion, and Hs is a Vickers hardness of the threaded portion.Type: ApplicationFiled: September 10, 2010Publication date: September 13, 2012Applicants: NATIONAL INSTITUTE FOR MATERIALS SCIENCE, KYOWA KOGYOSYO CO., LTD., FUSOKIKO CO., LTD.Inventors: Yuuji Kimura, Tadanobu Inoue, Shuji Murasaki, Mataichi Fukuda
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Publication number: 20120196210Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the mask, for determining a manufacturing penalty in making the mask. The manufacturability of the mask, including the manufacturing penalty in making the mask, is determined based on the target edge pairs as selected, and is dependent on the manufacturing penalty in making the mask. Determining the manufacturability of the mask includes, for a selected edge pair having first and second edges that are at least substantially parallel to one another, determining a manufacturing shape penalty owing to an aspect ratio of the first edge relative to a size of a gap between the first edge and the second edge. This penalty takes into account a pair of connected edges of the first edge that are at least substantially parallel to the first edge.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Inventors: Tadanobu Inoue, Alan E. Rosenbluth, Kehan Tian, David O. Melville, Masaharu Sakamoto
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Patent number: 8156331Abstract: Methods and apparatus are provided for securely inputting highly confidential information, exchanging the information via a network, and securely reflecting the information in a computer, without the information being stolen by malicious software. Upon a transfer of encrypted information from a server to a computer, the transferred information is stored in a memory of the computer and the computer is switched to a suspended state and immediately thereafter returns to the previous state to be shifted to under the control of a BIOS. The information stored in the memory is decrypted and processed there. Processing information generated based on the processed information is then encrypted and it is transferred to the server after the computer is switched to under the control of the operating system.Type: GrantFiled: July 18, 2007Date of Patent: April 10, 2012Assignee: Lenovo (Singapore) Pte. Ltd.Inventors: Seiichi Kawano, Tadanobu Inoue
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Patent number: 8149427Abstract: A raster-imaging processing (RIP) time is predicted for each of a number of pages to be printed in printed-page number order. The pages are sorted based at least on when RIP should be finished for each page. The pages are dispatched to RIP components for RIP at least substantially in an order in which the pages have been sorted. Each page is dispatched to a next RIP component that is available. A RIP component is available for a given page to be dispatched thereto where a total size of the RIP component's output buffer minus space within this output buffer taken up by any pages ordered after the given page in the printed-page number order is greater than the needed space to store the given page. The pages as have been raster-image processed are retrieved from the output buffers in the printed-page number order and transmitted to a printing device.Type: GrantFiled: April 26, 2007Date of Patent: April 3, 2012Assignee: InfoPrint Solutions Company, LLCInventors: Tadanobu Inoue, Kei Kawase
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Patent number: 8056026Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edges are selected from mask layout data of the lithographic mask. The mask layout data includes polygons distributed over cells, where each polygon has edges. The cells include a center cell, two vertical cells above and below the center cell, and two horizontal cells to the left and right of the center cell. Target edge pairs are selected for determining a manufacturing penalty in making the lithographic mask, in a manner that decreases the computational volume in determining the manufacturing penalty. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs selected. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.Type: GrantFiled: December 14, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O. Melville, Hidemasa Muta, Kehan Tian, Masahura Sakamoto, Alan E. Rosenbluth
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Patent number: 8056023Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.Type: GrantFiled: December 14, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O. Melville, Hidemasa Muta, Kehan Tian, Masahura Sakamoto, Alan E. Rosenbluth
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Patent number: 8028254Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.Type: GrantFiled: December 14, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Tadanobu Inoue, David O. Melville, Hidemasa Muta, Kehan Tian, Masaharu Sakamoto, Alan E. Rosenbluth
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Publication number: 20110231803Abstract: Optical wave data for a semiconductor device design is divided into regions. First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region and not accounting for the wave data of neighboring regions of each region. The optical wave data of each region is normalized based on results of the first wavefront engineering. Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as has been normalized. The second wavefront engineering takes into account the wave data of each region and a guard band around each region that includes the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed by organizing the regions into groups, and sequentially performing the second wavefront engineering on the regions of each group in parallel.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Inventors: Tadanobu Inoue, David O. Melville, Hidemasa Muta, Alan E. Rosenbluth, Kehan Tian, Masaharu Sakamoto, Saeed Bagheri