Patents by Inventor Tadao Nakamura

Tadao Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150131065
    Abstract: A foreign substance detection method includes: judging the presence/absence of a foreign substance by measuring a surface condition of a substrate; measuring a surface condition of a second substrate different from the substrate upon replacing the substrate on the chuck with the second substrate, when it is judged in the judging that a foreign substance exists; and determining whether an adhering location of the foreign substance determined to exist in the judging is the substrate, based on a measurement result obtained in the measurement.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 14, 2015
    Inventors: Tadao NAKAMURA, Yuji KOSUGI, Tomohisa NAKAZAWA
  • Patent number: 8949650
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: February 3, 2015
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20140344544
    Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Patent number: 8625069
    Abstract: An exposure apparatus the present invention comprises: an illumination optical system configured to illuminate an illumination area on an original with light from a light source; a projection optical system configured to project a pattern of the original onto a substrate; a first stage configured to hold the original; a second stage configured to hold the substrate; and a controller configured to control driving of at least one of the first stage, the second stage, and an optical element which forms the projection optical system so as to reduce variations in imaging characteristics of the projection optical system, based on a dependence of a transmittance of the pattern on a position in the illumination area.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: January 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Yabu, Tadao Nakamura
  • Publication number: 20120117412
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Application
    Filed: July 20, 2010
    Publication date: May 10, 2012
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20100302620
    Abstract: It is an object of the present invention to provide an electronic ink display device provided with a panel structure with excellent mechanical strength and humidity resistance. An electronic ink layer 13 is provided on a TFT substrate 10 through a lamination adhesive layer 12. The electronic ink layer 13 consists of micro capsules with electronic ink sealed therein contained in binders. A PET layer 16 including an ITO layer 15 is provided on the electronic ink layer 13. A TPA layer 11 is formed at one end of the electronic ink layer 13. A protect sheet 20 is provided on the PET layer 16 of FPL through a clear adhesive layer 17. The protect sheet 20 is provided with a humidity resistant barrier film 18 on one principal surface thereof through a clear adhesive layer 19.
    Type: Application
    Filed: April 20, 2005
    Publication date: December 2, 2010
    Inventors: Yasuyuki Makubo, Yuichiro Ohmae, Tomohiro Tsuji, Tadao Nakamura, Yoshikazu Hirota
  • Publication number: 20080316447
    Abstract: An exposure apparatus the present invention comprises: an illumination optical system configured to illuminate an illumination area on an original with light from a light source; a projection optical system configured to project a pattern of the original onto a substrate; a first stage configured to hold the original; a second stage configured to hold the substrate; and a controller configured to control driving of at least one of the first stage, the second stage, and an optical element which forms the projection optical system so as to reduce variations in imaging characteristics of the projection optical system, based on a dependence of a transmittance of the pattern on a position in the illumination area.
    Type: Application
    Filed: June 18, 2008
    Publication date: December 25, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Nobuhiko Yabu, Tadao Nakamura
  • Publication number: 20080252962
    Abstract: The invention provides an electronic ink display device having a panel structure of reduced thickness and enhanced moisture resistance and a method for manufacturing the same. The electronic ink display device has a first substrate (10) having display pixels, a second substrate (16) laid over the first substrate and having an electronic ink layer (13) on its lower major surface, the electronic ink layer having a space (26) terminating at a position with a predetermined distance receding from the periphery of the second substrate, and a seal (27) which fills the space and is laminated on the first substrate to cover at least part of the peripheral edge of the second substrate.
    Type: Application
    Filed: November 22, 2005
    Publication date: October 16, 2008
    Applicant: TPO Hong Kong Holding Limited
    Inventors: Yasuyuki Makubo, Tadao Nakamura, Tomohiro Tsuji, Yoshikazu Hirota, Yuichiro Ohmae
  • Patent number: 7191254
    Abstract: A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address of a program memory, an address data output section for outputting the address data in the address counter to the external device by use of a clock having a higher frequency provided from the external device than a clock for operating the microcomputer while applying a unit based on a bit number smaller than a bit number of the address data in the address counter.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 13, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Susumu Yamada, Tadao Nakamura, Susumu Kubota
  • Patent number: 7185117
    Abstract: Address data in an address counter is evaluated correctly. A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address in a program memory, an address data output section which outputs, to the external device, discrimination data for discriminating whether or not the address data in the address counter is one which is branched in order for the external device to store only branched address data, the discrimination data being outputted together with the address data.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 27, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Susumu Yamada, Tadao Nakamura, Susumu Kubota
  • Publication number: 20050060523
    Abstract: Address data in an address counter is evaluated correctly. A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address in a program memory, an address data output section which outputs, to the external device, discrimination data for discriminating whether or not the address data in the address counter is one which is branched in order for the external device to store only branched address data, the discrimination data being outputted together with the address data.
    Type: Application
    Filed: December 18, 2003
    Publication date: March 17, 2005
    Inventors: Susumu Yamada, Tadao Nakamura, Susumu Kubota
  • Publication number: 20050060615
    Abstract: A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address of a program memory, an address data output section for outputting the address data in the address counter to the external device by use of a clock having a higher frequency provided from the external device than a clock for operating the microcomputer while applying a unit based on a bit number smaller than a bit number of the address data in the address counter.
    Type: Application
    Filed: December 18, 2003
    Publication date: March 17, 2005
    Inventors: Susumu Yamada, Tadao Nakamura, Susumu Kubota
  • Patent number: 6106250
    Abstract: A lobed rotor-type pump has a drive shaft, a pump housing, an eccentric rotor journal, a rotor, three working-fluid chambers, intake and discharge ports, and a communication passage. The pump housing has a circumferentially-extending peri-trochoidal curved surface in its inner periphery. The eccentric rotor journal is fixedly connected to the drive shaft. The rotor is slideably fitted to the eccentric rotor journal. The rotor has three lobes equi-distantly spaced circumferentially around its outer periphery so that the rotor rotates eccentrically while keeping the lobes in sliding contact with the peri-trochoidal curved surface. The three working-fluid chambers, which are defined between respective three lobes and the peri-trochoidal curved surface, rotate in synchronism with the rotor. The intake and discharge ports are provided in the housing to input low-pressure incompressible fluid and to output high-pressure fluid.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: August 22, 2000
    Assignee: Unisia Jecs Corporation
    Inventors: Shoji Morita, Yasushi Watanabe, Tadao Nakamura
  • Patent number: 6066897
    Abstract: An automatic load distributing apparatus for generators is of simple construction and occupies a small space and can automatically distribute loads evenly on respective engines upon parallel load operation of generators of different capacities and provide labor saving of operation. The automatic load distributing apparatus for generators comprises a plurality of engines for driving a plurality of generators connected in parallel to a common load, a plurality of fuel injection pumps and a plurality of load distributing units for distributing outputs corresponding to the load to the engines.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: May 23, 2000
    Assignee: Komatsu Ltd.
    Inventor: Tadao Nakamura
  • Patent number: 5613474
    Abstract: A control method for starting a diesel engine makes it possible to prevent an excessive increase in fuel injection rate in a low speed rotation range at the time of starting for prevention of occurrence of misfiring and unstable engine rotation, and to prevent occurrence of black smoke by controlling the injection rate according to the engine temperature. For this effect, from the beginning of engine starting to a first engine rotating speed (N.sub.1), the control rack is moved in the fuel injection rate reducing direction so that the rack position has a first gradient to correct for an increase in fuel injection rate and, from the first engine rotating speed to a second engine rotating speed (N.sub.3) at which the control rack is returned to its position for ordinary control, the control rack is moved in the fuel injection rate reducing direction so that the rack position has a second gradient greater than the first gradient.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: March 25, 1997
    Assignee: Komatsu Ltd.
    Inventors: Tadao Nakamura, Makoto Watanabe, Tatsuro Nakazato
  • Patent number: D344943
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: March 8, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kajita, Takaharu Ando, Tadao Nakamura, Masahiko Happo
  • Patent number: D345157
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: March 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Happo, Tomiaki Shirakawa, Tadao Nakamura, Takato Yokouchi
  • Patent number: D345555
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: March 29, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takato Yokouchi, Takashi Kajita, Akihiko Konno, Tadao Nakamura
  • Patent number: D346382
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: April 26, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaharu Ando, Tadao Nakamura, Masahiko Happo, Tomiaki Shirakawa
  • Patent number: D355196
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: February 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadao Nakamura