Patents by Inventor Tadashi Kitamura

Tadashi Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170372464
    Abstract: A method of inspecting patterns to-be-inspected having regular intervals, the same widths and heights by using an image of the patterns to-be-inspected is disclosed. The method includes the steps of: obtaining centroids, widths and heights of the patterns to-be-inspected from an image of the patterns to-be-inspected; obtaining regular intervals, a mean of widths and a mean of heights of the patterns to-be-inspected, as information of design data, from the centroids, the widths and the heights; and inspecting the patterns to-be-inspected by using the information of the design data and edges of the image of the patterns to-be-inspected.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventor: Tadashi KITAMURA
  • Patent number: 9555516
    Abstract: A method for beveling a thin glass plate by simultaneously grinding an edge of the glass using multiple abrasive cup wheels, wherein the edge of the glass plate is extended from the fixturing device. The extension of the glass plate allows the glass plate to bend in response to forces applied by the abrasive cup wheels, thereby reducing the sensitivity of the grinding process to variations in position of the abrasive wheels. The axes of rotation of the abrasive wheels are separated by a distance selected to prevent deflection in the glass plate caused by a first abrasive wheel to influence the deflection in the glass plate caused by a second (adjacent) abrasive wheel.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 31, 2017
    Assignee: CORNING INCORPORATED
    Inventors: James W. Brown, Tadashi Kitamura, Gautam N. Kudva, Siva Venkatachalam
  • Patent number: 9459614
    Abstract: A machining condition estimating apparatus, and method, for estimating a machining condition to suppress a wear volume of a tool when conducting cutting work in a work machine are provided. For example, an analysis model presenting shapes of a tool and cutting material, may be defined, to be a target of analysis, and an initial value for use of analysis and change volume of the machining condition parameter as analysis parameters may be set up. Coordinates for tool and cutting material contact may be calculated. Moreover, a boundary movement rate, a maximum contact length, and a contact angle are calculated. A machining condition presented by the analysis parameter may also be searched and outputted.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: October 4, 2016
    Assignee: Hitachi Metals, Ltd.
    Inventors: Koji Utsumi, Shigeyoshi Fujihara, Tadashi Kitamura, Kenichi Inoue, Shinji Kayama
  • Patent number: 9189843
    Abstract: A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 17, 2015
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Toshiaki Hasebe, Masotoshi Tsuneoka
  • Publication number: 20140200709
    Abstract: A machining condition estimating apparatus, for estimating a long life-time machining condition, by suppressing boundary wears, from among plural numbers of choices of machining conditions, without building up database, comprise: a means for defining an analysis model presenting shapes of a tool and a cutting material, to be a target of analysis, and various kinds of machining condition parameters relating to relative positions between the tool and the cutting material; a means for setting up an initial value for use of analysis and change volume of the machining condition parameter as analysis parameters; a means for conducting geometric calculation of contact length, over which the tool and the cutting material of the model contact with, for each analysis parameter; a means for producing a distribution waveform, plotting the contact length “Lci” for each position “?i” of a point on each blade edge calculated, on “?i”?“Lci” coordinates, thereby to calculate a ratio of movement length of a boundary portion wi
    Type: Application
    Filed: January 15, 2014
    Publication date: July 17, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Koji UTSUMI, Shigeyoshi FUJIHARA, Tadashi KITAMURA, Kenichi INOUE, Shinji KAYAMA
  • Patent number: 8422761
    Abstract: Apparatus and method evaluate a wafer fabrication process for forming patterns on a wafer based upon design data. Within a recipe database, two or more inspection regions are defined on the wafer for analysis. Patterns within each of the inspection regions are automatically selected based upon tendency for measurement variation resulting from variation in the fabrication process. For each inspection region, at least one image of patterns within the inspection region is captured, a reference pattern, represented by one or both of (a) one or more line segments and (b) one or more curves, is automatically generated from the design data. An inspection unit detects edges within each of the images and registers the image with the reference pattern. One or more measurements are determined from the edges for each of the selected patterns and are processed within a statistical analyzer to form statistical information associated with the fabrication process.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: April 16, 2013
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Akio Ishikawa
  • Publication number: 20120328181
    Abstract: A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: NGR Inc.
    Inventors: Tadashi Kitamura, Toshiaki Hasebe, Masatoshi Tsuneoka
  • Patent number: 8285031
    Abstract: A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 9, 2012
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Toshiaki Hasebe, Masotoshi Tsuneoka
  • Publication number: 20120117520
    Abstract: A system and method for precise control of fine-line photolithography is disclosed. The system includes a wafer inspector that detects and measures edges and contours of patterns as produced on a wafer and a lithography simulator. The method calibrates the lithography simulator using multiple measurements and/or edges of patterns on the wafer. The calibrated lithography simulator is used to simulate processing to permit optimization of processing conditions by iterative adjustment and re-simulation. In embodiments, the process conditions optimized include one or more of dose, placement of edges on masks, and placement, shape, and locations of SRAF/OPC structures on the masks. In embodiments, the method includes using the calibrated lithography simulator to match results of production process equipment to those achieved with standard equipment. In embodiments, process data from multiple process simulations is stored in a single image file.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 10, 2012
    Inventors: Tadashi Kitamura, Akio Ishikawa
  • Patent number: 8150140
    Abstract: A system and method is described for evaluating a wafer fabrication process for forming patterns on a wafer based upon data. Multiple inspection regions are defined on the wafer for analysis. For each inspection region, images of patterns within the inspection region are captured, edges are detected, and lines are registered to lines of a reference pattern automatically generated from the design data. Line widths are determined from the edges. Measured line widths are analyzed to provide statistics and feedback information regarding the fabrication process. In particular embodiments defects are identified as where measured line widths lie outside boundaries determined from the statistics. In particular embodiments, lines of different drawn width and/or orientation are grouped and analyzed separately. Measured line widths may also be grouped for analysis according to geometry such as shape or proximity to other shapes in the inspection region to provide feedback for optical proximity correction rules.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: April 3, 2012
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Akio Ishikawa
  • Patent number: 8045785
    Abstract: A fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data is inspected by a pattern inspection apparatus. The pattern inspection apparatus for inspecting a pattern to-be-inspected uses an image of the pattern to-be-inspected and data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing edges of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: October 25, 2011
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Kazufumi Kubota, Shinichi Nakazawa, Neeti Vohra, Masahiro Yamamoto, Toshiaki Hasebe
  • Publication number: 20110235895
    Abstract: A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 29, 2011
    Applicant: NGR INC.
    Inventors: Tadashi Kitamura, Toshiaki Hasebe, Masotoshi Tsuneoka
  • Patent number: 7983471
    Abstract: A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: July 19, 2011
    Assignee: NGR Inc.
    Inventors: Tadashi Kitamura, Toshiaki Hasebe, Masatoshi Tsuneoka
  • Patent number: 7903230
    Abstract: A method for producing a liquid crystal display cell comprising processes of applying a sealing agent on a sealing portion of at least one liquid crystal display cell substrate, dropping liquid crystal on the substrate, and bonding substrates to each other under vacuum, wherein the sealing agent comprising a material to be cured and a curing agent is applied to the sealing portion without mixing the material to be cured and the curing agent, and then the substrates are bonded to each other under vacuum at room temperature to cure the sealing agent, is disclosed. A sealing agent for a liquid crystal display cell wherein the above material to be cured comprise a radically polymerizable resin and an organic peroxide, and the above curing agent comprises a radically polymerizable resin and a decomposition accelerator, is also disclosed.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: March 8, 2011
    Assignee: Mitsui Chemicals, Inc.
    Inventor: Tadashi Kitamura
  • Publication number: 20110021116
    Abstract: A method for beveling a thin glass plate by simultaneously grinding an edge of the glass using multiple abrasive cup wheels, wherein the edge of the glass plate is extended from the fixturing device. The extension of the glass plate allows the glass plate to bend in response to forces applied by the abrasive cup wheels, thereby reducing the sensitivity of the grinding process to variations in position of the abrasive wheels. The axes of rotation of the abrasive wheels are separated by a distance selected to prevent deflection in the glass plate caused by a first abrasive wheel to influence the deflection in the glass plate caused by a second (adjacent) abrasive wheel.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Inventors: James W. Brown, Tadashi Kitamura, Gautam N. Kudva, Siva Venkatachalam
  • Publication number: 20100303334
    Abstract: A fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data is inspected by a pattern inspection apparatus. The pattern inspection apparatus for inspecting a pattern to-be-inspected uses an image of the pattern to-be-inspected and data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing edges of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 2, 2010
    Inventors: Tadashi KITAMURA, Kazufumi KUBOTA, Shinichi NAKAZAWA, Neeti VOHRA, Masahiro YAMAMOTO, Toshiaki HASEBE
  • Patent number: 7817844
    Abstract: A pattern inspection apparatus is used for inspecting a pattern, such as semiconductor integrated circuit (LSI), liquid crystal panel, and a photomask by using an image of the pattern to-be-inspected and design data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device for generating a reference pattern represented by one or more lines from design data, an image generation device for generating the image of the pattern to-be-inspected, a detecting device for detecting an edge of the image of the pattern to-be-inspected, and an inspection device for inspecting the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: October 19, 2010
    Assignee: NanoGeometry Research Inc.
    Inventors: Tadashi Kitamura, Kazufumi Kubota, Shinichi Nakazawa, Neeti Vohra, Masahiro Yamamoto
  • Patent number: 7796801
    Abstract: A fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data is inspected by a pattern inspection apparatus. The pattern inspection apparatus for inspecting a pattern to-be-inspected uses an image of the pattern to-be-inspected and data for fabricating the pattern to-be-inspected.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: September 14, 2010
    Assignee: NanoGeometry Research Inc.
    Inventors: Tadashi Kitamura, Kazufumi Kubota, Shinichi Nakazawa, Neeti Vohra, Masahiro Yamamoto, Toshiaki Hasebe
  • Publication number: 20100215247
    Abstract: A system and method is described for evaluating a wafer fabrication process for forming patterns on a wafer based upon data. Multiple inspection regions are defined on the wafer for analysis. For each inspection region, images of patterns within the inspection region are captured, edges are detected, and lines are registered to lines of a reference pattern automatically generated from the design data. Line widths are determined from the edges. Measured line widths are analyzed to provide statistics and feedback information regarding the fabrication process. In particular embodiments defects are identified as where measured line widths lie outside boundaries determined from the statistics. In particular embodiments, lines of different drawn width and/or orientation are grouped and analyzed separately. Measured line widths may also be grouped for analysis according to geometry such as shape or proximity to other shapes in the inspection region to provide feedback for optical proximity correction rules.
    Type: Application
    Filed: March 16, 2010
    Publication date: August 26, 2010
    Inventors: Tadashi Kitamura, Akio Ishikawa
  • Publication number: 20100158345
    Abstract: Apparatus and method evaluate a wafer fabrication process for forming patterns on a wafer based upon design data. Within a recipe database, two or more inspection regions are defined on the wafer for analysis. Patterns within each of the inspection regions are automatically selected based upon tendency for measurement variation resulting from variation in the fabrication process. For each inspection region, at least one image of patterns within the inspection region is captured, a reference pattern, represented by one or both of (a) one or more line segments and (b) one or more curves, is automatically generated from the design data. An inspection unit detects edges within each of the images and registers the image with the reference pattern. One or more measurements are determined from the edges for each of the selected patterns and are processed within a statistical analyzer to form statistical information associated with the fabrication process.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 24, 2010
    Inventors: Tadashi Kitamura, Akio Ishikawa