Abstract: A thin film transistor device with its leakage current being controlled is provided. With such a thin film transistor device incorporated, a liquid crystal display apparatus presents a high-contrast image at a reduced power consumption. The thin film transistor is formed on an insulating substrate. The gate electrode of the transistor is electrically floating gate electrode, which is capacitance coupled to one or more input electrodes. The liquid crystal display apparatus incorporates the thin film transistor in its switching element and/or driving circuit.

Abstract: A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.

Abstract: A nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.The memory device comprises two or more semiconductor devices comprising a first MOS transistor having a first floating gate which is electrically insulated, a first electrode which is capacitively coupled with the first floating gate, a second electrode provided with the first floating gate via a tunnel junction, and a third electrode connected to the second electrode via a switch; the present invention is further provided with a fourth electrode connected commonly with the third electrodes of the semiconductor devices, a fifth electrode connected commonly with the source electrodes of the first MOS transistors, a sixth electrode which is capacitively coupled with the fourth electrode, and a seventh electrode which is connected with the fourth electrode via a switch.

Abstract: A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.

Abstract: A tire having a portion formed of a rubber composition which comprises a high-molecular-weight polymer component which contains bound styrene in an amount not greater than 30% by weight, is a styrene-butadiene copolymer or a conjugated diene polymer such as polybutadiene, and has a weight-average molecular weight of at least 30.times.10.sup.4 ; and a low-molecular-weight polymer component which contains bound styrene in an amount not greater than 30% by weight, is a styrene-butadiene copolymer or a conjugated diene polymer such as polybutadiene, and has a weight-average molecular weight of from 0.2.times.10.sup.4 to 8.times.10.sup.4. The rubber composition contains 30 parts by weight of the low-molecular-weight polymer component relative to 100 parts by weight of the high-molecular-weight polymer component. The ratio between the amount of bound styrene and the vinyl linkage content falls within specific ranges.

Abstract: The present invention has as an object thereof to provide a semiconductor operational circuit which is capable of instantaneously processing in parallel a large quantity of information. The semiconductor operational circuit of the present invention which executes a predetermined operation with respect to a first signal train of signals A.sub.1, A.sub.2, . . . , A.sub.N-1, A.sub.N (where N is a positive integer) of N signals numbered from 1 to N, and a second signal train of signals B.sub.1, B.sub.2, . . . , B.sub.M-1, B.sub.M (where M is a positive integer) of M signals numbered from 1 to M, comprising a plurality of first operational circuits for executing a predetermined operation with respect to A.sub.i, and B.sub.i+n (where i is a positive integer and n is a positive or negative integer and 1.ltoreq.i.ltoreq.n and 1.ltoreq.i+n.ltoreq.M) and generating an output signal C.sub.i,n, at least one second operational circuit for generating the sum S.sub.

Abstract: A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.

Abstract: A semiconductor integrated circuit includes one or more neuron MOS transistors on a substrate. The MOS transistor comprises a semiconductor region of one conductivity type, source and drain regions of opposite conductivity type disposed in this region, floating gate disposed on an insulating film between the source and drain regions, and a plurality of input coupling electrodes making capacitive coupling with the floating gate through the insulating film, wherein the floating gate is connected to at least one switching device.

Abstract: The present invention has as an object thereof to provide an intelligent electronical system which conducts the real-time recognition of real world data and makes decisions with respect to the data; that is to say, a computing circuit having an instantaneous recognition function and instantaneous recognition method.

Abstract: A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed.

Abstract: A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for the simultaneous input of the plurality of data, a mechanism for conducting a batch addition operation with respect to all the bits of the plurality of data, and for generating an analog or multi-valued signal having a linear relationship with the results of this addition and a mechanism for converting the analog or multi-valued signal to a digital signal. The plurality of data comprise bit data signals, and 4 or more of these are subjected to batch addition. A plurality of bit groups including a plurality of connected bits are also subjected to batch addition.

Abstract: A rubber composition having good breaking properties, high tan.delta., good wear resistance and a method for preparing a copolymer used in the rubber composition. The copolymer is a butadiene-styrene copolymer prepared in the presence of an organopotassium compound, an oxolanyl alkane and an organolithium initiator compound. The copolymer may be modified. A vulcanite of the rubber composition including 20 parts or more of the copolymer of the present invention has good properties.

Abstract: The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process.A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of conductivity as that of a semiconductor wafer provided on the back of the semiconductor wafer, and at least one layer of a low resistance electrode provided on said high concentration impurity layer.

Abstract: A semiconductor device has a semiconductor substrate, a source and a drain region, each formed at the surface of said semiconductor substrate, and each having a potential barrier with respect to the semiconductor substrate. A gate electrode is formed on the semiconductor substrate and positioned between the source and drain regions. The gate electrode controls the height of discrete energy levels of carriers of said semiconductor substrate, and provides a conduction state and a non-conduction state depending upon the existence or non-existence of resonant tunneling current flow.

Abstract: A device comprising invertor circuit group including two or more invertor circuits formed by neuron MOS transistors; means for applying a first signal voltage common to the two or more invertors of the invertor circuit group to a first input gate of the invertor circuit; means for applying a given second signal to one or more second input gates other than the first input gate of the invertor circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the invertor circuits of the invertor circuit group with a time delay generated by used of the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals by the ON and OFF of the transistor; and means for executing a given logical operation with respect to the output voltage signals generated by the invertor circuit group.

Abstract: Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished.The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.

Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s

Abstract: A transistor T26, serving as an output circuit 42, has a collector connected to a communication line B+ and an emitter connected to the other communication line B-. A base current generation circuit 44 generates a base current Ib for actuating transistor T26 based on a transmission signal. Transistors T24 and T25 constitute a current-mirror circuit. A correction circuit 46 takes in or absorbs a current equivalent to base current Ib from the collector of transistor T26, so as to equalize the drive currents IB+ and IB- flowing through twin communication lines B+ and B-. Since only one transistor T26 is used to actuate the twin communication lines B+ and B-, it, becomes possible to completely equalize the drive currents IB+ and IB- in their absolute values and to cause no phase dislocation between these two drive currents IB+ and IB-. Hence, the radio noises can be completely canceled when generated from each of twin communication lines B+ and B- due to change of currents flowing therethrough.

Abstract: The invention provides a semiconductor circuit which can fetch and store analog and multilevel data by using a simple circuit. The invention also provides a multilevel memory which can freely change the number of quantizing levels by using external signals. This semiconductor circuit comprises a first circuit which converts first signals into a group of quantized signals, a second circuit which converts the signal group into second multilevel signals, and structure which feeds back the second signals to the first circuit as first signals. The semiconductor circuit further has a structure to electrically separates at least one signal included in the signal group from the input of the second circuit, and structure which feeds back the second signals to the input of the second circuit instead of the signal previously separated.

Abstract: A non-volatile semiconductor memory which is capable of high speed and highly accurate analog data writing. The memory includes a first MOS type transistor having a first floating gate which is electrically isolated. A first electrode is capacitively coupled with the first floating gate. A second electrode is connected via a tunnel junction with the first floating gate. A third electrode is capacitively coupled with the second electrode. A second MOS type transistor interconnects the first and second electrodes. A means is provided for applying a predetermined potential difference between the first and third electrodes to thereby cause a tunnel current to flow in the tunnel junction and to store an electric charge in the first floating gate to thereby cause the second MOS type transistor to conduct when the electric charge has reached a predetermined value.