Patents by Inventor Tadashi Shibata

Tadashi Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4500905
    Abstract: Provided is a stacked semiconductor device wherein a plurality of semiconductor layers integrated with semiconductor elements are stacked with an insulating layer interposed between two adjacent of said semiconductor layers. This semiconductor device has one or more inclined faces extending over two or more of said semiconductor layers. These inclined faces are formed thereon with an interconnection layer or semiconductor element for effecting the transmission and reception of signals between circuits, having said semiconductor elements, formed in the different semiconductor layers, through another insulating layer.
    Type: Grant
    Filed: September 28, 1982
    Date of Patent: February 19, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Tadashi Shibata
  • Patent number: 4472874
    Abstract: A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a predetermined semiconductor element region of a semiconductor substrate; (b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; (c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; (d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; (e) burying insulation material in the groove; and (f) forming a semiconductor element on the predetermined semiconductor element region.
    Type: Grant
    Filed: June 3, 1982
    Date of Patent: September 25, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kei Kurosawa, Tadashi Shibata
  • Patent number: 4407851
    Abstract: A method of forming a flat field region in a semiconductor substrate, which comprises forming a recess in the substrate, forming a covering on the whole surface of the substrate with a first insulating film such as plasma CVD SiO.sub.
    Type: Grant
    Filed: December 29, 1981
    Date of Patent: October 4, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kei Kurosawa, Tadashi Shibata
  • Patent number: 4309224
    Abstract: A method for manufacturing a semiconductor device using a polycrystalline silicon layer as an electric conductive portion such as an electrode and/or conductor, which includes steps for doping the polycrystalline silicon layer with an impurity, and applying a radiation beam at least to part of the polycrystalline silicon layer after a heating step, thereby reducing the resistance of the polycrystalline silicon layer thereby to improve the operating speed of the device.
    Type: Grant
    Filed: September 25, 1979
    Date of Patent: January 5, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Tadashi Shibata
  • Patent number: 4267011
    Abstract: Disclosed is a method for manufacturing a semiconductor device using a polycrystalline silicon layer as an electrode and/or wire which includes a process for applying a laser light or electron beam to the polycrystalline silicon layer prior to a patterning process, thereby preventing over-etching and diffusion of impurity into the surface of a semiconductor substrate which are liable to be caused in the manufacturing processes, facilitating patterning in a desired manner, and reducing the resistance of the polycrystalline silicon layer to improve the operating speed of the device.
    Type: Grant
    Filed: September 20, 1979
    Date of Patent: May 12, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tadashi Shibata, Hisakazu Iizuka
  • Patent number: 4140547
    Abstract: A method for manufacturing an MOS FET includes a step of forming a p.sup.+ -type layer in a p-type substrate by injecting ions into the substrate through a field oxide film using a mask layer and removing the portion of the field oxide film under the mask layer.
    Type: Grant
    Filed: September 8, 1977
    Date of Patent: February 20, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Tadashi Shibata, Nozomu Harada
  • Patent number: 4113064
    Abstract: An elevator car mounting arrangement for an elevator of the type comprising a car for carrying passengers or freight mounted in a framework hung by a wire rope and guided in its ascent and descent along guide rails fixed to a shaft. The car is arranged such that it can oscillate freely in a horizontal direction whereby the transversal vibration of the car can be prevented.
    Type: Grant
    Filed: November 29, 1973
    Date of Patent: September 12, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Shigeta, Tadashi Shibata
  • Patent number: 3991856
    Abstract: In an elevator including weight-compensating ropes having their respective one end connected to the lower end of a car and the other end thereof connected to the lower end of a counterweight, an oscillation-absorbing device is provided closely adjacent to at least one of a first connecting portion of the main ropes to a car or the counterweight and a second connecting portion of the weight-compensating ropes to the car or counterweight, thereby absorbing oscillation energy from ropes.
    Type: Grant
    Filed: January 25, 1974
    Date of Patent: November 16, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Shigeta, Tadashi Shibata, Toshihiko Nara
  • Patent number: 3945468
    Abstract: A sound preventive device for use in an elevator including: a skirt extending from the lower edge of the sill of a cage of an elevator and having a length greater than the difference between the height of the floor and the height of the cage and a width substantially the same as that of the cage; and guide plates which extend upwards and downwards respectively from the rear plate of the cage, the aforesaid guide plates having widths substantially the same as that of the rear plate, whereby abrupt changes in air developing above and below the cage may be minimized by means of the skirt and guide plates.
    Type: Grant
    Filed: December 11, 1974
    Date of Patent: March 23, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Miura, Ken Ichiryu, Masayuki Shigeta, Tadashi Shibata