Patents by Inventor Tae Ahn

Tae Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5834405
    Abstract: A superconducting multilayer ceramic substrate is disclosed, prepared by firing a laminate of at least two polymer bonded cast sheets of a ceramic dielectric oxide powder, at least one sheet of which has a metallization pattern provided thereon, to thereby form a superconducting oxide reaction layer at the interface between the sintered ceramic material and the embedded metallic conductor lines of the metallization pattern.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: November 10, 1998
    Assignee: International Business Machines Corporation
    Inventors: Byung Tae Ahn, Robert Bruce Beyers, Emanuel Israel Cooper, Edward August Giess, Eugene John O'Sullivan, Judith Marie Roldan, Lubomyr Taras Romankiw
  • Patent number: 5822355
    Abstract: A dual cavity laser having a positively mode-locked structure capable of double increasing the repetition rate of output light. The dual cavity laser includes an amplitude modulator to simultaneously generate two modulating signals with opposite phases. The dual cavity laser has a simply modified structure from that of the conventional single cavity laser to have two resonators, so that it can have a repetition rate corresponding to two times that of the single cavity laser. One of the resonators may have an adjusted optical property so as to obtain two kinds of output optical pulses with different optical properties.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: October 13, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon-Tae Ahn, Kyu-Seok Lee, El-Hang Lee
  • Patent number: 5790579
    Abstract: A pulsed semiconductor laser has a lower threshold current and a more stable pulse train. The structure includes a saturable absorber section has a quantum well structure for laser oscillation, a gain section, a phase control section, and a super structure grating-distributed Bragg reflector section. It uses an improved construction for overcoming problems of conventional pulsed semiconductor lasers. The improved structure includes five quantum well layers having thicknesses with respective spontaneous emission peak wavelengths of ".lambda.-2.delta.", ".lambda.+.delta.", ".lambda.+2.delta.", ".lambda.", ".lambda.-.delta." at room temperature from their upper section. .lambda. denotes the mean wavelength of the oscillating pulse laser, and .delta. denotes a fixed value less than 12 nm.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: August 4, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyu-Seok Lee, Joon-Tae Ahn, El-Hang Lee
  • Patent number: 5567645
    Abstract: An improved method for performing a local oxidation of silicon (LOCOS) capable of forming a sufficient thickness of a field oxide film even in narrow isolation regions. After defining the isolation region, a first field oxide film is formed in the isolation region by means of a first field oxidation. A film formed of HTO, LTO or SOG, or a pre-oxide film formed of polysilicon is formed on the resultant product. Then, the film, oxide film or the pre-oxide film is removed by anisotropically etching with a dry etching process or a chemical mechanical process so as to be left only in the isolation region, which after a second field oxidation forms a second field oxide film.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: October 22, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-tae Ahn, Tai-su Park
  • Patent number: 5360753
    Abstract: In an element isolation method of a semiconductor device which can form an element isolation region having a flat surface without regard to the width of the element isolation region, and whose width is below the resolution limit, an insulating film having an aperture in order to define the element isolation region is formed on the semiconductor wafer, wherein an oxidizable material layer is deposited and then first spacers are formed on the sidewalls of the aperture. Then, a thermal oxide film is formed over the entire semiconductor wafer, excluding a first-spacer-formed region, and the first spacer is removed. The wafer surface is exposed to the lower part of the removed first spacer region, and then the portion of the semiconductor wafer below the exposed region is etched to thereby form a trench. After that, an element isolation region is formed by filling up the trench and removing the insulating film around tile trench.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: November 1, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-seo Park, Yun-gi Kim, Dong-chul Park, Sung-tae Ahn, Byeong-yeol Kim