Patents by Inventor Tae Cho

Tae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7830279
    Abstract: An apparatus for inputting characters and method thereof are disclosed, by which a character can be inputted at high speed in a manner of implementing a new character set and by which a character can be inputted at high speed using a new character set and a rotatable moving key. The present invention includes an input unit comprising a plurality of roller type keys, each generating a rotation-associated keying signal or a pressing-associated keying signal and a plurality of selection keys, each generating the pressing-associated keying signal and a controller performing a character set search by a character set unit according to the rotation-associated keying signal, the controller performing a character input according to the pressing-associated keying signal.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: November 9, 2010
    Assignee: LG Electronics Inc.
    Inventor: Sung Tae Cho
  • Patent number: 7794347
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. Furthermore, the method of operating the power train is varied depending on the transmission gear ratio, so that the power train can be operated with superior efficiency.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 14, 2010
    Assignee: Hyundai Motor Company
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Nam-Wook Kim, Ho-Rim Yang
  • Publication number: 20100211992
    Abstract: A data security apparatus fragments original data into a plurality of data, blocks the fragmented data, and distributes and stores the blocked data over and in respective storage medium. The data security apparatus includes a storage having a first block, into which original data of a file is fragmented and blocked, distributed and stored, a security storage medium having a second block, into which the original data is fragmented and blocked, distributed and stored, and a distributed storage management module performing data interface among the storage, the security medium, and an operating system (OS) system, fragmenting and blocking the original data, and distributing and storing the blocked data over and in the storage and the security storage medium.
    Type: Application
    Filed: September 12, 2008
    Publication date: August 19, 2010
    Applicant: MILLENNIUM FORCE CO. LTD
    Inventors: Yong Tae Cho, Kyoung Mu Ryu
  • Publication number: 20100159640
    Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 24, 2010
    Applicant: JUSUNG ENGINEERING CO., LTD.
    Inventors: Sang Ki PARK, Seong Ryong HWANG, Geun Tae CHO
  • Publication number: 20100140220
    Abstract: In forming a pattern on a substrate with reduced pattern error using a mold having an area smaller than an area of the substrate, a first resin pattern is formed on at least a first of a plurality of regions of an etching object layer by imprinting resin applied to the etching object layer using a first mold The etching object layer is then etched using the first resin pattern as an etching mask. A second resin pattern is formed on at least a second of the plurality of regions by imprinting resin applied to the etching object layer using a second mold. The etching object layer is again etched using the second resin pattern as an etching mask.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 10, 2010
    Inventors: Young Tae Cho, Suk Won Lee, Sin Kwon, Jung Woo Seo, Jeong Gll Kim
  • Publication number: 20100096770
    Abstract: A manufacturing process using a replica mold for nano imprinting having a grid type pattern by combining a nano imprint with a dry etching process is disclosed. In order to attain such a manufacturing process, a method of fabricating a mold for nano imprinting may include arranging a master mold having first patterns over a substrate having metal patterns so that both the first pattern and the metal pattern cross over each other, applying resin between the master mold and the substrate, applying an imprinting treatment of the substrate as well as the master mold, hardening the resin, and etching the hardened resin after the master mold is released, so as to form a replica mold for nano imprint. The nano imprinting process and the etching process may easily form a pattern in a more complicated structure, and therefore, may improve production yield and reduce processing time thereof.
    Type: Application
    Filed: September 28, 2009
    Publication date: April 22, 2010
    Inventors: Young Tae Cho, Jeong Gil Kim
  • Patent number: 7691021
    Abstract: A power train having dual modes for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. The method of operating the power train varies depending on the transmission gear ratio, and thus the power train can be operated with superior efficiency.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: April 6, 2010
    Assignee: Hyundai Motor Company
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Ho-Rim Yang
  • Publication number: 20100072675
    Abstract: Example embodiments relate to a method of forming a three-dimensional micro pattern or a multi-step pattern using a nano imprinting process and a method of manufacturing a mold to form such a pattern. A molding polymer may be patterned in a one-step shape on a substrate having UV barrier patterns, thereby easing the manufacture of a mold for multi-step imprinting and simplifying the formation of a multi-step pattern using the one-step shaped mold by avoiding the repetition of more complicated processes. Consequently, it may be possible to form a relatively large-area micro pattern, a relatively large-area pattern usable in flat panel displays, and a nano pattern having a size of several tens of nanometers in a semiconductor process, thereby contributing to the reduction of process costs, the reduction of process time, and the improvement of production yield.
    Type: Application
    Filed: May 28, 2009
    Publication date: March 25, 2010
    Inventors: Young Tae Cho, Young Suk Sim, Jeong Gil Kim
  • Publication number: 20100072245
    Abstract: Disclosed is a substrate alignment apparatus capable of performing coarse and fine alignments of a substrate in a progressing route to remove or reduce an alignment error between the substrate and a pattern roll. The coarse alignment may be performed by moving a frame using a stage when the alignment error is relatively large, and the fine alignment may be performed by moving subsidiary rollers of a roller unit relative to a main roller of a roller unit when the alignment error is relatively small. An example substrate alignment apparatus may include a frame and a roller unit rotatably fixed to the frame to support a substrate, wherein the roller unit includes a main roller, and at least one subsidiary roller fixed to the main roller such that the at least one subsidiary roller can move relative to the main roller to align the substrate.
    Type: Application
    Filed: July 30, 2009
    Publication date: March 25, 2010
    Inventors: Dong Min Kim, Sin Kwon, Young Tae Cho, Jung Woo Seo, Ki Keon Yeom, Ki Hyun Kim
  • Publication number: 20100072661
    Abstract: Disclosed herein are a method of manufacturing various replica molds for nano imprint using nano imprint and etching and a method of forming a multi-step pattern or a micro pattern through a nano imprint process using the manufactured replica molds for nano imprint. A pattern forming method using nano imprint may include applying a mold resin between a substrate having a first pattern patterned thereon and a master mold with a second pattern patterned thereon, aligning the substrate and the master mold to imprint a pattern, curing the mold resin, separating the master mold from the substrate, and etching the cured mold resin to manufacture a replica mold for nano imprint. The method may also include forming an imprint resin on a forming substrate, pressing the replica mold into the imprint resin, curing the imprint resin, separating the replica mold from the imprint resin, and washing the first imprint resin.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 25, 2010
    Inventors: Young Tae Cho, Jeong Gil Kim
  • Patent number: 7659215
    Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: February 9, 2010
    Assignee: Korea Research Institute of Chemical Technology
    Inventors: Chang-Gyoun Kim, Young-Kuk Lee, Taek-Mo Chung, Ki-Seok An, Sun-Sook Lee, Won-Tae Cho
  • Publication number: 20100025806
    Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.
    Type: Application
    Filed: December 30, 2008
    Publication date: February 4, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
  • Patent number: 7642161
    Abstract: A method of fabricating a semiconductor device includes forming an isolation structure in a substrate to define an active region, forming a recess mask pattern over the isolation structure and the active region, etching the isolation structure exposed by the recess mask pattern to a certain depth, etching the substrate to form a recess pattern, and forming a gate electrode over the recess pattern.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: January 5, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20090213008
    Abstract: A multiple RF receiver and locating method using the same have developed. The multiple RF receiver includes: a clock generator for generating a clock according to multiple RF receiving modules included in a multiple RF receiving unit; a phase distributor for dividing the clock into clocks having different phases, and providing the clocks to the multiple RF receiving unit as clock sources; the multiple RF receiving unit for generating SFD (Start of Frame Delimiter) signals by using the phases of the clocks provided as the clock sources; and a time measuring unit for measuring the SFD signals for use as data for location measurement.
    Type: Application
    Filed: January 27, 2009
    Publication date: August 27, 2009
    Inventors: Yun-Ju Paek, Hyun-Tae Cho, Hyun-Sung Jang
  • Patent number: 7575974
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Suk-Ki Kim, Yong-Tae Cho
  • Patent number: 7553767
    Abstract: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: June 30, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20090163010
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 25, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Rok OH, Hyun-Sik PARK, Yong- Tae CHO
  • Publication number: 20090130841
    Abstract: A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.
    Type: Application
    Filed: June 27, 2008
    Publication date: May 21, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae CHO, Jae-Kyun LEE, Sang- Rok OH
  • Publication number: 20090087960
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae CHO, Eun-Mi Kim
  • Publication number: 20090077732
    Abstract: A height adjusting water saving urinal adapted to be connected to a flush toilet system, includes a bowl, a top opening, a bottom opening, a bottom drain opening, an extendable urinal, a connecting device and a seat that is provided on the top opening so that a female user can sit on the seat. The bowl has a basin, a top portion, and a bottom portion. The top opening is provided at the top portion of the bowl. The bottom drain opening is provided at the bottom portion of the bowl. The extendable urinal drain pipe extends from the bottom drain opening. The connecting device, provided at an end of the extendable urinal drain pipe, is for connecting the urinal to the flush toilet system. The extendable urinal drain pipe shares the main drain pipe of the flush toilet.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventor: Tae Cho KANG