Patents by Inventor Tae Cho

Tae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070135262
    Abstract: A control system of a starting motor for an automatic transmission vehicle includes a starting switch having a plurality of nodes and an ignition key for connecting the plurality of nodes to a battery, a position sensor detecting a shift lever position and generating a pulse width modulation signal corresponding thereto, a shift control module receiving the pulse width modulation signal from the position sensor and generating a starting control signal, and a starting relay electrically connected to the starting switch and the shift control module and applying the battery power to the starting motor, wherein the shift control module generates the starting control signal if the shift lever position is a P position or an N position.
    Type: Application
    Filed: August 21, 2006
    Publication date: June 14, 2007
    Inventor: Tae Cho
  • Publication number: 20070072389
    Abstract: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.
    Type: Application
    Filed: June 20, 2006
    Publication date: March 29, 2007
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20070004181
    Abstract: A method for fabricating a region in which a fuse is formed is provided. The method includes forming a first insulation layer over a substrate, forming a plurality of fuses over the first insulation layer, forming a second insulation layer to cover the fuses, forming an etch stop layer over the second insulation layer, forming a metal layer over a predetermined portion of the etch stop layer, forming a third insulation layer to cover the metal layer, performing a pad/repair process on the third insulation layer until the metal layer and the etch stop layer are exposed, and selectively removing the exposed portion of the etch stop layer and the second insulation layer.
    Type: Application
    Filed: February 27, 2006
    Publication date: January 4, 2007
    Inventors: Yong-Tae Cho, Hae-Jung Lee
  • Publication number: 20070004194
    Abstract: A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.
    Type: Application
    Filed: December 30, 2005
    Publication date: January 4, 2007
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Sang-Hoon Cho
  • Patent number: 7037778
    Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch stop layer; forming a plurality of contact plugs on the plurality of contact holes such that the contact plugs are more projected than the first etch stop layer; sequentially forming a second etch stop layer and a capacitor insulation layer; forming a plurality of openings by etching the second etch stop layer and the capacitor insulation layer to expose the contact plugs; sequentially forming a storage node material and a sacrificial layer; etching the storage node material and the sacrificial layer, thereby obtaining isolated storage node material; and removing remaining portions of the sacrificial layer and the capacitor insulation layer.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Yong-Tae Cho
  • Patent number: 7004884
    Abstract: Shift performance of a powertrain system of a hybrid electric vehicle is enhanced by a powertrain system including a clutch, a primary motor, an automated shift gearbox (ASG) connected to the engine interposing the clutch, a secondary motor; and a differential gearbox, wherein the primary motor is disposed between an output shaft of the clutch and an input shaft of the ASG, and the secondary motor is disposed between an output shaft of the ASG and an input shaft of the differential gearbox.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: February 28, 2006
    Assignee: Hyundai Motor Company
    Inventor: Sung Tae Cho
  • Publication number: 20060035606
    Abstract: Disclosed is a method and apparatus for transmitting and outputting data in voice communication over a traffic channel. The apparatus includes: a signal generator for generating a low frequency signal corresponding to a key signal inputted during voice communication; a signal synthesizer for synthesizing the low frequency signal and a voice signal; a radio communication unit for transmitting the synthesized signal over the traffic channel; a signal separator for separating a low frequency signal from a signal received and processed by the radio communication unit; and a data output unit for detecting a frequency of the separated low frequency signal and outputting data indicated by the detected frequency.
    Type: Application
    Filed: May 17, 2005
    Publication date: February 16, 2006
    Applicant: Pantech&Curitel Communications, Inc.
    Inventor: Gi-Tae Cho
  • Publication number: 20060003539
    Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch stop layer; forming a plurality of contact plugs on the plurality of contact holes such that the contact plugs are more projected than the first etch stop layer; sequentially forming a second etch stop layer and a capacitor insulation layer; forming a plurality of openings by etching the second etch stop layer and the capacitor insulation layer to expose the contact plugs; sequentially forming a storage node material and a sacrificial layer; etching the storage node material and the sacrificial layer, thereby obtaining isolated storage node material; and removing remaining portions of the sacrificial layer and the capacitor insulation layer.
    Type: Application
    Filed: December 20, 2004
    Publication date: January 5, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventor: Yong-Tae Cho
  • Publication number: 20050130020
    Abstract: Fuel cell including an electrolyte, an anode and a cathode on both sides of the electrolyte, a cathode side separator at an outer side of the cathode having a flow passage for flow of air, and a flow passage between the electrolyte and the anode, thereby improving an electricity generating performance.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 16, 2005
    Inventors: Sam Ha, Tae Cho, Myung Park, Hong Choi, Cheol Kim, Myeong Lee, Seoug Heo, Seung Ko
  • Publication number: 20050003581
    Abstract: There are disclosed a stacked package formed by stacking semiconductor device packages and a manufacturing method thereof. Each package includes leads and connection terminals. A semiconductor chip is electrically connected to the connection terminals. A package body has the same thickness as that of the lead so as to expose the upper and the lower surfaces of the leads to the package body. Each of the packages is stacked on another package by electrically connecting the exposed upper and lower surfaces of the leads with each other. The manufacturing method has preparing lead frames, attaching an adhesive tape to the lower surface of the lead frame, bonding a semiconductor chip to the adhesive tape in the chip receiving cavity between the leads, connecting the semiconductor chip to the connection terminals, forming a package body, removing the adhesive tape; removing dam bars from the side frame, separating packages from the lead frame, and forming a stacked package by stacking a plurality of the packages.
    Type: Application
    Filed: July 29, 2004
    Publication date: January 6, 2005
    Inventors: Ju Lyu, Kwan Lee, Tae Cho
  • Patent number: 6566188
    Abstract: A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: May 20, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Hyun Kim, Bong Ho Choi, Yong Tae Cho
  • Publication number: 20020197813
    Abstract: A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.
    Type: Application
    Filed: June 21, 2002
    Publication date: December 26, 2002
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Hyun Kim, Bong Ho Choi, Yong Tae Cho
  • Publication number: 20010039561
    Abstract: Disclosed is a method for notifying message reception to a personal computer by Email when the message is received in the voice mail system through an exchange using a voice mail service function. The method includes the steps of: registering an E-mail address in the voice mail system using a phone; storing the voice message received at the voice mail system; determining whether an E-mail notification function is set; transmitting corresponding voice message information to the registered E-mail address of the E-mail server if the E-mail notification function is set; transmitting an attached file of the received voice message to the personal computer of the E-mail subscriber with the registered E-mail address, and displaying the attached file on a message window of the personal computer in order to notify message reception in the voice mail system; and, reproducing, using the personal computer, the received message in sound when the user opens the attached file displayed on the message window.
    Type: Application
    Filed: December 1, 2000
    Publication date: November 8, 2001
    Applicant: SAMSUNG ELECTRONIC CO., LTD.
    Inventor: Yi-Tae Cho
  • Patent number: 6276756
    Abstract: A height adjusting assembly for chairs. The assembly includes a first member having a taper holder positioned near an opening/closing pin and a taper arm engaged with the taper holder so as to push the opening/closing pin. A second member having a case, a lead arm engaged with the case and a button which operates the lead arm. A third member having a wire in which one end is connected to the taper arm and the other end is connected to the lead arm and a covering member in which one end is connected to the taper holder and the other end is connected to the case so that the wire is slidable in the covering member and the opening/closing pin is pushed by an operation of the taper arm which is engaged with the wire when the lead arm is operated by the button. The pushing force of the button can be controlled by the length of the taper arm and the rod arm. The height of a chair is adjusted easily and conveniently as the button is installed in the arm resting member of a chair.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: August 21, 2001
    Assignee: Samhongsa Co. Ltd.
    Inventors: Yong Tae Cho, Song Hur
  • Patent number: D394900
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: June 2, 1998
    Inventor: Tae Cho Kang