Patents by Inventor Tae Cho

Tae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7507651
    Abstract: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Suk-Ki Kim
  • Patent number: 7496974
    Abstract: A height adjusting water saving urinal adapted to be connected to a flush toilet system, includes a bowl, a top opening, a bottom opening, a bottom drain opening, an extendable urinal, a connecting device and a seat that is provided on the top opening so that a female user can sit on the seat. The bowl has a basin, a top portion, and a bottom portion. The top opening is provided at the top portion of the bowl. The bottom drain opening is provided at the bottom portion of the bowl. The extendable urinal drain pipe extends from the bottom drain opening. The connecting device, provided at an end of the extendable urinal drain pipe, is for connecting the urinal to the flush toilet system. The extendable urinal drain pipe shares the main drain pipe of the flush toilet.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 3, 2009
    Inventor: Tae Cho Kang
  • Patent number: 7481733
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. Furthermore, the method of operating the power train varies depending on the transmission gear ratio, and thus the power train can be operated with superior efficiency.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: January 27, 2009
    Assignee: Hyundai Motor Company
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Kuk-Hyun Ahn
  • Publication number: 20080299467
    Abstract: Disclosed are a mask mold, a manufacturing method thereof, and a method for forming a large-sized micro pattern using the manufactured mask mold, in which the size of a nano-level micro pattern can be enlarged using a simple method with low cost and interference and stitching errors between cells forming a large area can be minimized. The method for manufacturing the mask mold includes the operations of coating resist on a mask or a plurality of small molds having an engraved micro pattern, pressing the small molds to imprint the micro pattern on the resist, curing the resist, and releasing the small molds from the resist.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Gil Kim, Young Tae Cho, Young Suk Sim, Sung Hoon Cho, Suk Won Lee, Seon Mi Park, Sin Kwon, Jung Woo Seo, Jung Woo Park, Sung Woo Cho
  • Publication number: 20080182072
    Abstract: Provided is a substrate for forming a pattern comprising an inorganic layer having a modified surface, wherein the modified surface is formed by coating a surface of the inorganic layer with a bifunctional molecule comprising a functional group having an affinity for a nanocrystal at one end of the molecule and a functional group having an affinity for the inorganic layer at the other end of the molecule. A method for forming a pattern of nanocrystals is also provided.
    Type: Application
    Filed: June 1, 2007
    Publication date: July 31, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Jae Choi, Kyung Sang Cho, Jae Young Choi, Dong Kee Yi, Hyeon Jin Shin, Seon Mi Yoon, In Young Song, Jong Hyeon Lee, Duk Young Jung, Geun Tae Cho
  • Publication number: 20080160742
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a first recess pattern by etching the substrate and a sidewall protection layer on sidewalls of the first recess pattern, forming a second recess pattern having a greater width than the first recess pattern by etching a certain portion of the substrate below a bottom portion of the first recess pattern, and forming a gate electrode filling the first and the second recess patterns.
    Type: Application
    Filed: December 24, 2007
    Publication date: July 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong-Tae CHO, Hae-Jung LEE
  • Publication number: 20080113500
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.
    Type: Application
    Filed: June 26, 2007
    Publication date: May 15, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Suk-Ki KIM, Yong-Tae CHO
  • Publication number: 20080102624
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to form passivation layers on the sidewalls of the first recess wherein the passivation layers are comprised of an etch reactant of the first etching process, and performing a second etching process on the substrate below the first recess to form a second recess.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 1, 2008
    Inventors: Yong-Tae Cho, Suk-Ki Kim
  • Publication number: 20080102639
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 1, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong-Tae CHO, Suk-Ki KIM, Sang-Hoon CHO
  • Publication number: 20080081449
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic etching on the second trench pattern to round sidewalls of the second trench pattern and form a bulb pattern, and forming a gate over a recess pattern including the first trench pattern, the rounded second trench pattern and the bulb pattern.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Inventors: Yong-Tae Cho, Jae-Seon Yu
  • Publication number: 20080054332
    Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: Korea Research Institute of Chemical Technology
    Inventors: Chang-Gyoun KIM, Young-Kuk LEE, Taek-Mo CHUNG, Ki-Seok AN, Sun-Sook LEE, Won-Tae CHO
  • Publication number: 20080039261
    Abstract: A power delivery system of a hybrid vehicle includes: a planetary gear part disposed including a first planetary gear, a second planetary gear, and a third planetary gear; a driving motor/generator part including a first motor/generator connected to the third planetary gear such that a power delivery can be performed therebetween, and a second motor/generator configured to deliver power to a driving shaft via the second planetary gear and supporting an engine in a starting state so as to operate the driving shaft; a clutch part connected to the planetary gear part such that the hybrid vehicle can drive by changing the operation mode at at least a critical mechanical point wherein the mechanical power of the driving motor/generator part is zero; and a controller controlling operations of the driving motor/generator part and the clutch part.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 14, 2008
    Inventors: Sung Tae CHO, Jang Moo LEE, Nam Wook KIM
  • Publication number: 20080003748
    Abstract: A method of fabricating a semiconductor device includes forming an isolation structure in a substrate to define an active region, forming a recess mask pattern over the isolation structure and the active region, etching the isolation structure exposed by the recess mask pattern to a certain depth, etching the substrate to form a recess pattern, and forming a gate electrode over the recess pattern.
    Type: Application
    Filed: December 26, 2006
    Publication date: January 3, 2008
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20080003791
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a substrate to form a first recess, etching the substrate at side portions of the first recess to form a second recess, and forming a gate insulation layer and a gate electrode over the second recess, wherein etching the substrate to form the second recess includes performing an isotropic etching process.
    Type: Application
    Filed: December 26, 2006
    Publication date: January 3, 2008
    Inventors: Yong-Tae Cho, Phil-Goo Kong
  • Publication number: 20070287564
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. The method of operating the power train varies depending on the transmission gear ratio, and thus the power train can be operated with superior efficiency.
    Type: Application
    Filed: December 4, 2006
    Publication date: December 13, 2007
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Ho-Rim Yang
  • Publication number: 20070287565
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. Furthermore, the method of operating the power train varies depending on the transmission gear ratio, and thus the power train can be operated with superior efficiency.
    Type: Application
    Filed: December 26, 2006
    Publication date: December 13, 2007
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Kuk-Hyun Ahn
  • Publication number: 20070225099
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. Furthermore, the method of operating the power train is varied depending on the transmission gear ratio, so that the power train can be operated with superior efficiency.
    Type: Application
    Filed: December 28, 2006
    Publication date: September 27, 2007
    Inventors: Sung-Tae Cho, Jang-Moo Lee, Nam-Wook Kim, Ho-Rim Yang
  • Publication number: 20070184927
    Abstract: A power train for hybrid vehicles increases the range of the transmission gear ratio within which the efficiency of the power train is superior. Furthermore, the method of operating the power train varies depending on the transmission gear ratio, and thus the power train can be operated with superior efficiency.
    Type: Application
    Filed: December 26, 2006
    Publication date: August 9, 2007
    Inventor: Sung-Tae Cho
  • Publication number: 20070148934
    Abstract: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.
    Type: Application
    Filed: April 27, 2006
    Publication date: June 28, 2007
    Inventors: Yong-Tae Cho, Suk-Ki Kim
  • Publication number: 20070148979
    Abstract: A method for forming a semiconductor device having a recess pattern with a rounded top corner is provided. The method includes forming an etch mask pattern including a patterned sacrificial layer and a patterned hard mask layer over a substrate; etching predetermined portions of exposed sidewalls of the patterned sacrificial layer to form an undercut; etching the substrate to a predetermined depth using the etch mask pattern as an etch mask to form a recess having top corners; and performing an isotropic etching process to round the top corners of the recess beneath the undercut.
    Type: Application
    Filed: April 28, 2006
    Publication date: June 28, 2007
    Inventors: Hae-Jung Lee, Yong-Tae Cho