Abstract: In a MEA (membrane electrode assembly) of a fuel cell including an electrolyte membrane as an ion transfer medium arranged between a bipolar plate having a fuel side open groove in which fuel flows and a bipolar plate having an air side open groove in which air flows so as to form a fuel path with the fuel side open groove and form an air path with the air side open groove; and a catalyst electrode inserted into the fuel side open groove so as to be separated from the electrolyte membrane in order to form a fuel path with both sides thereof and induce electrochemical oxidation with the fuel, by activating action occurred on the fuel electrode in which fuel is supplied and the air electrode in which air is supplied, current generating efficiency can be improved.

Abstract: A reflecting type liquid crystal display device having a perpendicularly aligned structure and shorter response time and a projector using the same are provided. The reflecting type liquid crystal display device includes a first substrate having a reflective electrode, a second substrate having a transparent electrode, first and second alignment layers provided on the first substrate and the second substrate to be opposed to and face each other, a spacer interposed between the first alignment layer and the second alignment layer to form a predetermined cell gap therebetween, and vertically aligned liquid crystals injected into the cell gap, the cell gap being not greater than 1.0 ?m, the dielectric anisotropy of the liquid crystals being negative value, and the refractive index anisotropy of the liquid crystals being not less than 0.14.

Abstract: A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: Disclosed is a signal processing circuit which outputs a digital word corresponding to a current source controlled by a physical response. The signal processing circuit includes an analog integrated circuit for generating an analog signal in response to a time varying reference signal and a signal corresponding to the current source controlled by the physical response, a reference signal generator for generating a reference signal, a comparator for comparing the analog signal with the reference signal, an output circuit for generating the digital word indicating a time interval defined by a start signal and an end signal indicating a transition of an output of the comparator, and a controller inactivating the comparator in response to the end signal.

Abstract: A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.

Abstract: A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.

Abstract: A nonvolatile semiconductor memory device includes a program state detection circuit for checking a state of programmed memory cells. The program state detection circuit checks program pass/fail using data transmitted through a column selection circuit, according to a column address having redundancy information. Therefore, it is possible to overcome the problem that the memory device is regarded as a fail device owing to a defective column.

Abstract: A method for processing messages in a multiuser dungeon operating on a computer system connected with other computer systems via a network eliminates message conflicts due to network time delays.