Patents by Inventor Tae-Hong Min
Tae-Hong Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12262467Abstract: A printed circuit board includes a first insulating layer, a first pattern buried in a surface of the first insulating layer, the first pattern having a surface exposed from the surface of the first insulating layer, and a metal post disposed on the exposed surface of the first pattern. The metal post includes a first metal layer and a second metal layer. The first metal layer and the second metal layer include different metals.Type: GrantFiled: February 24, 2023Date of Patent: March 25, 2025Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong Min, Eun Su Kwon
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Publication number: 20250048553Abstract: A printed circuit board includes a first substrate portion including a first insulating portion and a plurality of first wiring layers respectively disposed on or in the first insulating portion, a resin layer disposed to cover a side surface of the first insulating portion, and a second substrate portion including a second insulating portion disposed to cover each of an upper surface of the first insulating portion and an upper surface of the resin layer, and a second wiring layer disposed on or in the second insulating portion.Type: ApplicationFiled: June 18, 2024Publication date: February 6, 2025Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong MIN, Sang Hoon KIM
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Patent number: 12219692Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.Type: GrantFiled: November 22, 2023Date of Patent: February 4, 2025Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung Byun, Jung Soo Kim, Sang Hyun Sim, Chang Min Ha, Tae Hong Min, Jin Won Lee
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Patent number: 12183718Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: January 10, 2024Date of Patent: December 31, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
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Publication number: 20240365467Abstract: The present disclosure relates to a printed circuit board include: a core layer including an inorganic insulating layer, a resin layer covering at least a portion of an external side surface of the inorganic insulating layer, and a second insulating layer covering at least a portion of a lower surface of each of the inorganic insulating layer and the resin layer and having an interlayer boundary with the resin layer; a first wiring layer disposed on an upper surface of the core layer; and a second wiring layer disposed on a lower surface of the core layer. The external side surface of the inorganic insulating layer is substantially perpendicular to at least one of the upper surface and the lower surface of the inorganic insulating, and a manufacturing method therefor.Type: ApplicationFiled: January 9, 2024Publication date: October 31, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong MIN, Jong Eun PARK
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Publication number: 20240215157Abstract: A printed circuit board includes: a first insulating layer; a via pad disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a via hole exposing at least a portion of an upper surface of the via pad; a conductor pattern disposed on the exposed upper surface of the via pad; and a via including a first metal layer covering at least a portion of each of a wall surface of the via hole, the exposed upper surface of the via pad, and the conductor pattern, and a second metal layer disposed on the first metal layer and disposed in at least a portion of the via hole.Type: ApplicationFiled: October 20, 2023Publication date: June 27, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ki Ran PARK, Hyun Woo KWON, Tae Hong MIN, Sang Hyun HAN, Guh Hwan LIM, Yo Han SONG, Dong Keun LEE, Kyeong Yub JUNG, Eun Gyu JEONG, Yu Mi KIM
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Publication number: 20240145437Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
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Publication number: 20240090121Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung BYUN, Jung Soo KIM, Sang Hyun SIM, Chang Min HA, Tae Hong MIN, Jin Won LEE
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Publication number: 20240057251Abstract: A printed circuit board includes a first insulating layer, a first pattern buried in a surface of the first insulating layer, the first pattern having a surface exposed from the surface of the first insulating layer, and a metal post disposed on the exposed surface of the first pattern. The metal post includes a first metal layer and a second metal layer. The first metal layer and the second metal layer include different metals.Type: ApplicationFiled: February 24, 2023Publication date: February 15, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong Min, Eun Su Kwon
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Patent number: 11894346Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: March 10, 2023Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
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Publication number: 20240032208Abstract: A printed circuit board includes a first build-up insulating layer; an interconnect structure buried in an upper side of the first build-up insulating layer and including one or more insulating layers, one or more wiring layers, and one or more via layers; an adhesive disposed between an upper surface of the first build-up insulating layer and an upper surface of the interconnect structure, and having an upper surface exposed from the upper surface of the first build-up insulating layer; and a metal bump including a via portion penetrating the adhesive and a protrusion protruding to the upper surface of the adhesive.Type: ApplicationFiled: March 1, 2023Publication date: January 25, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong MIN, Eun Su KWON
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Patent number: 11864307Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.Type: GrantFiled: December 17, 2020Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung Byun, Jung Soo Kim, Sang Hyun Sim, Chang Min Ha, Tae Hong Min, Jin Won Lee
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Publication number: 20230420285Abstract: A substrate processing apparatus includes: a stage including a first region and a second region surrounding the first region, the stage configured to receive a substrate; and a plurality of pins in or on the stage and configured to adsorb the substrate with negative pressure. The plurality of pins include a plurality of first pins in the first region and are configured to be elevated at the same time, and a plurality of second pins in the second region and are configured to be elevated at the same time. In operation, the first pins are elevated and adsorb the substrate first, and then, the second pins are elevated and adsorb the substrate.Type: ApplicationFiled: May 10, 2023Publication date: December 28, 2023Inventors: Hyung Jun Choi, Tae Hong Min
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Patent number: 11769622Abstract: Disclosed is an inductor device and method of manufacturing the same. The inductor device includes an insulating layer, a coil pattern formed on two opposing surfaces of the insulating layer, a first insulating film and a second insulating film formed with different insulating materials on the coil pattern, and a magnetic member formed to enclose the insulating layer, the coil pattern and the first and the second insulating films. By forming thin dual insulating films having a high adhesive strength and breaking strength on an inductor coil, it is possible to improve Ls characteristics of the inductor device and increase the inductance.Type: GrantFiled: December 27, 2018Date of Patent: September 26, 2023Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: In-Seok Kim, Yong-Jin Park, Young-Gwan Ko, Youn-Soo Seo, Myung-Sam Kang, Tae-Hong Min
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Patent number: 11737211Abstract: A connection structure embedded substrate includes: a printed circuit board including a plurality of first insulating layers and a plurality of first wiring layers, respectively disposed on or between the plurality of first insulating layers; and a connection structure disposed in the printed circuit board and including a plurality of internal insulating layers and a plurality of internal wiring layers, respectively disposed on or between the plurality of internal insulating layers. Among the plurality of internal wiring layers, an internal wiring layer disposed in one surface of the connection structure is in contact with one surface of a first insulating layer, among the plurality of first insulating layers.Type: GrantFiled: July 9, 2021Date of Patent: August 22, 2023Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hong Min, Ho Hyung Ham, Yong Soon Jang, Ki Suk Kim, Hyung Ki Lee, Chi Won Hwang
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Publication number: 20230262891Abstract: A connection structure embedded substrate includes: a printed circuit board including a plurality of first insulating layers and a plurality of first wiring layers, respectively disposed on or between the plurality of first insulating layers; and a connection structure disposed in the printed circuit board and including a plurality of internal insulating layers and a plurality of internal wiring layers, respectively disposed on or between the plurality of internal insulating layers. Among the plurality of internal wiring layers, an internal wiring layer disposed in one surface of the connection structure is in contact with one surface of a first insulating layer, among the plurality of first insulating layers.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hong Min, Ho Hyung Ham, Yong Soon Jang, Ki Suk Kim, Hyung Ki Lee, Chi Won Hwang
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Publication number: 20230207533Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: March 10, 2023Publication date: June 29, 2023Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
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Publication number: 20230187360Abstract: A substrate includes: a first printed circuit board layer including a first insulating layer and a first wiring layer, disposed on a lower surface of the first insulating layer; a second wiring layer, disposed on an upper surface of the first insulating layer; a bridge disposed above the first printed circuit board layer and including circuit wirings; a first bridge insulating layer and a second bridge insulating layer, disposed in the bridge and on which the circuit wirings are disposed, respectively; and a second printed circuit board layer including a second insulating layer surrounding side surfaces of the bridge and covering the first insulating layer and the second wiring layer. A first stacking direction in which the first insulating layer and the second insulating layer are stacked and a second stacking direction in which the first bridge insulating layer and the second bridge insulating layer are stacked are different.Type: ApplicationFiled: May 20, 2022Publication date: June 15, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Tae Hong Min
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Patent number: 11664352Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: May 24, 2021Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
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Patent number: 11558961Abstract: A printed circuit board includes a first insulating layer having a through hole, and a via disposed to fill the through hole and to be extended to at least one surface of the first insulating layer, wherein the via includes a plating layer having an inner wall part disposed on an inner wall of the through hole and a land part extended from the inner wall part and disposed on the at least one surface of the first insulating layer, and a metal paste layer including metal particles, and filled in the rest of the through hole and disposed on the plating layer.Type: GrantFiled: October 24, 2019Date of Patent: January 17, 2023Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jungwoo Choi, Tae-hong Min