Abstract: A coil component according to an aspect of the present disclosure includes a coil component having a body including a first surface and a second surface opposing each other in a first direction, and a third surface and a fourth surface connecting the first surface to the second surface and opposing each other in a second direction; a coil disposed in the body; an external electrode disposed on the body and connected to the coil; and a first heat dissipation portion disposed on the first surface, wherein the body includes a groove disposed in a region between the first heat dissipation portion and the external electrode.

Abstract: A semiconductor memory device includes: a substrate including a cell area, a peripheral area, and a boundary area; a storage pad connected to an active area in the cell area; a capacitor including a lower electrode, a first electrode support layer supporting the lower electrode, a capacitor dielectric, and an upper electrode; a peripheral gate on the peripheral area of the substrate; first peripheral contact plugs on both sides of the peripheral gate and connected to the substrate; a first interlayer insulating layer on the storage pad and the first peripheral contact plugs; a second interlayer insulating layer on the first interlayer insulating layer; and a first insulating layer on the second interlayer insulating layer, wherein the first insulating layer extends on the boundary area of the substrate, and a height of the first insulating layer is equal to or less than a height of the first electrode support layer.

Abstract: The present disclosure provides an apparatus for treating a substrate. The apparatus includes a chuck supporting the substrate, a gas supply unit configured to supply a process gas to an edge region of the substrate, and an edge electrode provided to surround the substrate supported by the chuck when viewed from a top and configured to generate plasma from the gas, in which the edge electrode has a ring shape and a groove recessed from an inner circumference of the edge electrode to an outer circumference of the edge electrode when viewed from the top is formed in the edge electrode.

Abstract: The present disclosure relates to a motor including a motor housing, a stator provided in the motor housing, a coil wound around the stator, a rotor rotatably provided inside the stator, a water-cooled cooling part provided in the motor housing and including a water jacket configured to define a coolant flow path through which a coolant circulates, and an oil-cooled cooling part provided in the motor housing and configured to spray cooling oil to the coil, thereby obtaining an advantageous effect of improving cooling performance, stability, and reliability.

Abstract: A semiconductor chip includes a substrate. a device layer and an interconnection layer sequentially on the substrate, and a bonding pad on the interconnection layer. A bottom surface of the bonding pad may be located at a constant level, and a side surface of the bonding pad may have a roughened shape.

Abstract: Proposed are a deep trench capacitor and a method of manufacturing the same that compensate for a thin thickness in bottom corner areas of an oxide film (e.g., SiO2) grown by thermal oxidation in a deep trench to prevent a deterioration in breakdown voltage characteristics due to electric field concentration in the corner areas of the oxide film, or that relatively flatten widthwise inner sidewalls of the deep trench to improve the breakdown voltage characteristics and gap-fill characteristics of a device.

Abstract: Disclosed herein is a method for managing memory in a memory disaggregation environment. The method includes handling a required subblock within a block more preferentially than an additional block in the event of a page fault and handling a page fault for the block in which the required subblock is preferentially processed.

Abstract: The present disclosure relates to a pharmaceutical composition comprising chiral nanozyme and method of preventing or treating proliferative diseases using the same. A first nanozyme and/or a second nanozyme according to embodiments of the present disclosure has a chiral structure, and their enzymatic activity is maximized when circularly polarized light with the same directionality as the first nanozyme and/or the second nanozyme is irradiated.

Abstract: A semiconductor package may include a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a second semiconductor chip horizontally spaced apart from the first semiconductor chip, a mold layer provided on the first redistribution substrate to enclose the first and second semiconductor chips, a second redistribution substrate disposed on the mold layer, a connection member, which is provided at a side of the first and second semiconductor chips to connect the first redistribution substrate to the second redistribution substrate, and an antenna substrate attached to the second redistribution substrate using an adhesive layer. The antenna substrate may include a core portion, an antenna pattern provided on a top surface of the core portion, and a wiring pattern provided on a bottom surface of the core portion.

Abstract: A display device includes a substrate including a display area and a driving circuit area, a first insulating layer, a second insulating layer on the first insulating layer, a first transistor in the display area, and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer, and a second transistor in the driving circuit area, and including a second semiconductor pattern layer formed as the semiconductor layer, a second gate electrode on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, wherein the first lower electrode is between the substrate and the first insulating layer, and the second lower electrode is between the first insulating layer and the second insulating layer.

Abstract: A method for manufacturing a semiconductor device includes extracting coordinates of vertices of patterns from an optical proximity corrected layout data for an optical proximity corrected layout including the patterns; and inputting the coordinates of the vertices into a transformer model to output whether there is a Mask Rule Check (MRC) violation on the optical proximity corrected layout data.

Abstract: A display device that includes a substrate; a circuit layer; and an element layer. The substrate may include a display area in which emission areas may be arranged, and a non-display area. In order to deliver data signals to data lines at side edges of the display area, bypass auxiliary lines are used that pass through central portions of the display area to allow for a reduced width of the sub area. A horizontal portion of these bypass auxiliary lines may pass over or under other data lines to reach the edge portion of the display. Therefore, a shielding auxiliary electrode may be disposed between the passed over data lines and the horizontal bypass auxiliary lines at locations where these other data lines overlap in a plan view the horizontal bypass auxiliary lines to reduce crosstalk between the horizontal bypass auxiliary lines and the data lines.

Abstract: A processor-implemented method includes receiving at least one information comprising either one or both of control information of a vehicle and environment information of the vehicle; determining a driving situation of the vehicle, based on the at least one information; changing control parameters for changing a waveform of radar sensors of a sensing system, based on the determined driving situation of the vehicle, wherein the control parameters comprise an operation mode comprising a chirp mode of the radar sensors and comprise sensor parameters of the radar sensors; and transmitting the changed control parameters to the sensing system in real time.

Abstract: A lighting apparatus for a vehicle, the lighting apparatus including: a rear panel; a printed circuit board (PCB) disposed in front of the rear panel and including a plurality of lighting sources; a rubber pad disposed in front of the PCB and configured to a plurality of through-holes formed based on positions of the plurality of lighting sources; a front panel snap-fitted to the rear panel; and a light guide member coupled to an accommodating space formed between a plurality of first buttons and a plurality of second buttons disposed on the front panel, wherein the light guide member includes a transmission member through which light emitted from the plurality of lighting sources transmits and a shielding member shielding the light.

Abstract: Disclosed are a method and apparatus for estimating a camera pose. The method includes dividing an input image received from a camera into a plurality of regions, dividing the plurality of regions into a first detection zone for detecting a vanishing point or a roll and a second detection zone for detecting the roll, extracting a representative feature from features of the input image by using a filter generated in advance for each of the plurality of regions based on a design value of the camera, calculating a feature error of each of the first detection zone and the second detection zone based on the representative feature, and estimating a pose of the camera based on the feature error.

Abstract: A coil electronic component includes a main body; a coil embedded in the main body, an insulating layer disposed on one surface of the main body, a first conductive layer covering a portion of the one surface, a second conductive layer covering another portion of the one surface, and first and external electrodes respectively covering the first conductive layer. The coil electronic component has a first length L1 in a first direction, and a second length L2 is a sum of a third length L3 in the first direction of a region where the insulating layer, the first conductive layer, and the first external electrode overlap and a fourth length L4 in the first direction of a region where the insulating layer, the second conductive layer, and the second external electrode overlap. A ratio L2/L1 is 0.3 or more and 0.7 or less.

Abstract: A testing apparatus for a power module includes a first socket board including a first withstand voltage test pin, a second socket board including a second withstand voltage test pin and a DC test pin, a tester configured to generate a withstand voltage test signal and transmit the withstand voltage test signal to the first withstand voltage test pin and the second withstand voltage test pin, and to generate a DC test signal and transmit the DC test signal to the DC test pin, and a relay closing or opening an electrical connection between the tester and at least one of the first withstand voltage test pin, the second withstand voltage test pin, and the DC test pin.

Abstract: A control method of a mobile terminal includes receiving content information and device information, receiving a content selection signal and a device selection signal from a user, generating a control command for controlling a content corresponding to the content selection signal, and transmitting the control command to a host. The control command includes a change command for switching a selected device to another device to output a selected content continuously.

Abstract: A pellicle assembly may include a pellicle membrane and a pellicle border. The pellicle membrane may include at least one recess and at least one opening. The at least one recess may extend from an upper surface or a lower surface of the pellicle membrane. The at least one opening may penetrate from the upper surface to the lower surface of the pellicle membrane. The pellicle border may support the pellicle membrane.

Abstract: A semiconductor device may include a substrate, a plurality of cell strings perpendicular to an upper surface of the substrate, and a bit line connected to at least six of the cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. A first one of the first to fourth selection ground selection transistors may have a first threshold voltage distribution, and a second one of the first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.