Patents by Inventor Tae Jin Kang
Tae Jin Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9058859Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.Type: GrantFiled: September 14, 2012Date of Patent: June 16, 2015Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Publication number: 20150016196Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.Type: ApplicationFiled: September 18, 2014Publication date: January 15, 2015Inventors: Kyoung Hwan KWON, Tae Jin KANG, Sang Kwon LEE
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Patent number: 8896340Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.Type: GrantFiled: September 13, 2012Date of Patent: November 25, 2014Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Publication number: 20140320437Abstract: One or more embodiments provide a method for processing and an electronic device. The display method of the electronic device can include the operations of, if a damage of a touchscreen sensing a gesture is sensed, confirming a region in which the damage of the touchscreen does not occur. The display method can also include changing the size of an output screen based on the region in which the damage of the touchscreen does not occur. The display method can also include outputting the size-changed output screen to the region in which the damage of the touchscreen does not occur. Other example embodiments are also possible.Type: ApplicationFiled: April 25, 2014Publication date: October 30, 2014Applicant: Samsung Electronics Co., Ltd.Inventor: Tae-Jin Kang
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Patent number: 8867302Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.Type: GrantFiled: April 28, 2011Date of Patent: October 21, 2014Assignee: SK Hynix Inc.Inventors: Kyoung Hwan Kwon, Tae Jin Kang, Sang Kwon Lee
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Patent number: 8854903Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.Type: GrantFiled: January 24, 2012Date of Patent: October 7, 2014Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Publication number: 20140226421Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: Conversant IP N.B. 868 Inc.Inventor: Tae-Jin KANG
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Publication number: 20140176167Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.Type: ApplicationFiled: March 18, 2013Publication date: June 26, 2014Applicant: SK HYNIX INC.Inventors: Young Suk SEO, Ho Uk SONG, Jun Hyun CHUN, Tae Jin KANG
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Patent number: 8705312Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.Type: GrantFiled: May 21, 2013Date of Patent: April 22, 2014Assignee: 658868 N.B. Inc.Inventor: Tae-Jin Kang
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Patent number: 8699279Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.Type: GrantFiled: December 23, 2011Date of Patent: April 15, 2014Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Patent number: 8692585Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.Type: GrantFiled: September 23, 2011Date of Patent: April 8, 2014Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Patent number: 8658399Abstract: Disclosed herein is a novel gluconacetobacter strain having cellulose producing activity. Specifically, the present invention relates to a novel gluconacetobacter strain producing nano-structured cellulose in a highly efficient manner. The cellulose produced by the strain, due to its superb thermodynamic properties, can be characterized as nano-structured bacterial cellulose and therefore utilized as a bio-nano-fiber. Particularly, the cellulose can be impregnated with a resin to form a cellulose-based resin which can be effectively adapted for a substrate for a liquid crystal display (LCD).Type: GrantFiled: October 29, 2012Date of Patent: February 25, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jong-Seong Kim, Woo-jae Lee, Nam-Seok Roh, Sang-Il Kim, Min-Ho Yoon, Young Tak Song, Tae Jin Kang, Suk Heung Oh, Seung-Jae Lee, Hye Jin Kim, Jin Ju Yu, Dong Hyun Yu, Young Sik Yoon, Jong Hwan Lee
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Patent number: 8610460Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.Type: GrantFiled: August 21, 2012Date of Patent: December 17, 2013Assignee: SK Hynix Inc.Inventor: Tae Jin Kang
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Publication number: 20130272541Abstract: A mobile communication device and a method of setting tone color, which allow a user to set the tone color of received sound. Provided are a normal mode, which sets the equalizer using GCF standards stored in an internal memory or equalizer setting values selected by a provider, a country-specific mode, which uses country-specific setting, and a user mode, in which a user can set frequency-specific gains of the received sound, and one mode is selected from the provided mode, so that the tone color of the received sound can be adjusted according to the selection. Telephone speech quality can be optimized for user preference, network environments and language characteristics.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventor: Tae-Jin Kang
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Publication number: 20130257474Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.Type: ApplicationFiled: September 13, 2012Publication date: October 3, 2013Applicant: SK hynix Inc.Inventor: Tae Jin KANG
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Publication number: 20130250705Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.Type: ApplicationFiled: May 21, 2013Publication date: September 26, 2013Applicant: 658868 N.B. INC.Inventor: Tae-Jin KANG
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Publication number: 20130222009Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.Type: ApplicationFiled: August 21, 2012Publication date: August 29, 2013Applicant: SK HYNIX INC.Inventor: Tae Jin KANG
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Patent number: 8505474Abstract: The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.Type: GrantFiled: July 30, 2008Date of Patent: August 13, 2013Assignee: SNU R&DB FoundationInventors: Tae Jin Kang, Byung Duck Kim, Young Seung Chi, Jung Sim Roh
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Publication number: 20130176797Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.Type: ApplicationFiled: September 14, 2012Publication date: July 11, 2013Applicant: SK HYNIX INC.Inventor: Tae Jin KANG
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Patent number: 8483408Abstract: A mobile communication device and a method of setting tone color, which allow a user to set the tone color of received sound. Provided are a normal mode, which sets the equalizer using GCF standards stored in an internal memory or equalizer setting values selected by a provider, a country-specific mode, which uses country-specific setting, and a user mode, in which a user can set frequency-specific gains of the received sound, and one mode is selected from the provided mode, so that the tone color of the received sound can be adjusted according to the selection. Telephone speech quality can be optimized for user preference, network environments and language characteristics.Type: GrantFiled: September 16, 2008Date of Patent: July 9, 2013Assignee: Samsung Electronics Co,. Ltd.Inventor: Tae-Jin Kang