Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract: The present invention relates to a objective measurement of fabric pillings, to a measurement apparatus which includes stereovision technique using CCD cameras, captures the 3-dimensional contours of fabric pilling and defines the degree of pilling occurrences. This invention is composed of; a step to scan the surface of a pilling-containing fabric specimen which is laid on the table and translated in the right angle of the projector laser beam; a step to reconstruct the scanned fabric surface data in to a 3D image; a step to convert the 3D image into a binary image using height-threshold method and number, area, density of pillings acquired from standard pictures; a step to calculate the x, y coordinates and height values of each and every area of the specimen; a step to regress the relationship between the height values of the pilling fabric specimen and the actual height values.

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: Disclosed herein is a differential amplifier control circuit in which a signal indicating that all banks are not activated is provided to a differential amplifier, so that the differential amplifier does not operate, thereby reducing unnecessary current consumption in an ICC2N situation. An all bank idle notification unit generates an all bank idle signal notifying that a plurality of banks are not activated using a plurality of bank active signals for activating the plurality of the banks. A differential amplifier controller generates a differential amplifier control signal for disabling a differential amplifier using an all bank idle signal and an internal clock signal. The differential amplifier does not operate in response to the differential amplifier control signal if the plurality of the banks is all inactivated.

Abstract: A clock enable buffer for entry of a self-refresh mode. The clock enable buffer includes a current mirror load connected between a voltage source and first and second nodes, wherein the current mirror load has first and second transistors; a third transistor connected between the first node and a third node, wherein the third transistor is turned on according to a reference voltage; a fourth transistor connected between the second node and the third node, for controlling the current mirror load in response to a clock enable signal; a fifth transistor connected between the third node and a ground, wherein the fifth transistor is turned on according to a self-refresh signal; and a sixth transistor that is turned on according to an inverted self-refresh signal to make the potential of the first node a Low level.

Abstract: A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The bank selecting control unit outputs a test mode control signal for selecting a test mode in response to a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection in the parallel test. Each of the plurality of bank selecting units, which correspond one by one to banks, selectively activates the corresponding banks in response to the test mode control signal and a bank selecting control signal.

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract: The present invention relates to a objective measurement of fabric pillings, to a measurement apparatus which includes stereovision technique using CCD cameras, captures the 3-dimensional contours of fabric pilling and defines the degree of pilling occurrences. This invention is composed of; a step to scan the surface of a pilling-containing fabric specimen which is laid on the table and translated in the right angle of the projector laser beam; a step to reconstruct the scanned fabric surface data in to a 3D image; a step to convert the 3D image into a binary image using height-threshold method and number, area, density of pillings acquired from standard pictures; a step to calculate the x, y coordinates and height values of each and every area of the specimen; a step to regress the relationship between the height values of the pilling fabric specimen and the actual height values.

Abstract: The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

Abstract: A method for forming an inner cylinder type storage electrode of a semiconductor memory device, comprising the steps of: forming a first insulating layer on a substrate; etching the first insulating layer to form a contact hole, thereby exposing a portion of the substrate; forming a conductive film for a storage electrode over the first insulating layer including the contact hole; forming a photosensitive film in a portion of the contact hole over the conductive film; forming a second insulating layer to be completely filled in the contact hole over the photosensitive film; etching the second insulating layer and the conductive film to expose the first insulating layer, thereby forming the storage electrode; and removing the first and second insulating layers and the photosensitive film.