Patents by Inventor Tae Joo

Tae Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200407764
    Abstract: The present disclosure relates to a method for preparing a fermented composition, and more specifically, to a method for preparing a fermented composition with improved odor, which comprises preparing grain flour; performing primary fermentation of the grain flour using yeast; performing secondary fermentation of the primary fermented product using a strain of the genus Bacillus; and obtaining the secondary fermented product. The fermented composition of the present disclosure has a high content of a peptide with a low molecular weight, and thus enables the increase of digestibility and absorption rate of proteins during ingestion while also improving the peculiar odor of a fermented product to enhance its palatability.
    Type: Application
    Filed: February 14, 2019
    Publication date: December 31, 2020
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: HyoJeong Seo, Tae Joo Yang, Hyun Chi, Myeong-hyeon Choi, Seung Won Park, YoungHo Hong
  • Publication number: 20200383364
    Abstract: The present disclosure relates to a method for preparing a transglucosylated steviol glycoside using a crude enzyme liquid of a Lactobacillus mali strain.
    Type: Application
    Filed: December 14, 2018
    Publication date: December 10, 2020
    Inventors: Tae Joo YANG, Young Mi LEE, In Sung KANG, Sunghee PARK, Young Su LEE, Sun CHU, Seong Bo KIM, Eun Jung CHOI
  • Patent number: 10821127
    Abstract: The present invention relates to a method for inhibiting myeloid-derived suppressor cells or treating cancer comprising administering a pharmaceutical composition containing decitabine or its pharmaceutically acceptable salt as an active ingredient. The decitabine suppresses creation of a cell population of myeloid-derived suppressor cells (MDSC) created in spleen and bone marrow in tumorigenic mice and induces apoptosis of the MDSC cell population. Therefore, the decitabine may be useful as agents for treating MDSC-related diseases and anticancer immunotherapy, or an anticancer supplement.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 3, 2020
    Assignee: SHAPERON INC.
    Inventors: Seung-Yong Seong, Jung Ah Cho, Tae Joo Kim, Hyeon Park
  • Publication number: 20200343219
    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
  • Patent number: 10787250
    Abstract: Provided is a multi-copter, including: a fuselage; three or more intermediate supporting bars which have one ends fixed to the fuselage and radially extend from the fuselage; two mounting rods which are divided into two branches at the other ends of the intermediate supporting bars; and a propeller set configured by two propellers which are mounted to two mounting rods and rotate at the same rotational speed (RPM) in opposite directions. When an angle formed by any one propeller between two propellers which form the propeller set and the mounting rod is a first angle and an angle formed by the other one propeller and the mounting rod is a second angle, a difference between the first angle and the second angle is 360/2n degrees and n is a number of blades for every propeller.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Korea Aerospace Research Institute
    Inventor: Tae Joo Kim
  • Patent number: 10784030
    Abstract: Provided herein is a magnetic sheet. The magnetic sheet according to one embodiment of the present invention includes a magnetic layer formed of crushed pieces of a magnetic body to improve flexibility of the magnetic sheet, and a thin film coating layer formed on at least one surface of the magnetic layer to maintain the magnetic layer in a sheet shape and buffer an external force applied to the crushed pieces of the magnetic body.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: September 22, 2020
    Assignee: AMOGREENTECH CO., LTD.
    Inventors: Jin Hyoung Lee, Hyun Tae Joo, Chol Han Kim
  • Publication number: 20200291443
    Abstract: The present disclosure relates to a method for preparing a transfructosylated steviol glycoside using Arthrobacter-derived microorganisms, a culture thereof, a supernatant of the culture, an extract of the culture, and a lysate of the microorganisms.
    Type: Application
    Filed: October 25, 2018
    Publication date: September 17, 2020
    Applicant: CJ Cheiljedang Corporation
    Inventors: Tae Joo Yang, In Sung Kang, Min Hoe Kim, Sunghee Park, Sun Chu, Seong Bo Kim, Young Mi Lee, Young Su Lee, Eun Jung Choi
  • Publication number: 20200277700
    Abstract: A method for manufacturing a transition metal-dichalcogenide thin film is provided. The method for manufacturing a transition metal-dichalcogenide thin film can comprise the steps of: preparing a base substrate within a chamber; preparing a precursor comprising a transition metal; repeatedly carrying out, multiple times, a step of providing the precursor on the base substrate and a step of purging the chamber, thereby forming, on the base substrate, a preliminary thin film in which the precursor is adsorbed; and manufacturing a transition metal-dichalcogenide thin film by heat treating the preliminary thin film in a gas atmosphere comprising a chalcogen element.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Tae Joo Park, Dae Hyun Kim, Daewoong Kim, Tae Jun Seok, Hyunsoo Jin
  • Patent number: 10727199
    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
  • Patent number: 10665575
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Publication number: 20200027862
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok SONG, Chan-kyung KIM, Tae-joo HWANG
  • Publication number: 20200009703
    Abstract: The present invention relates to a substrate polishing system comprising a polishing pad covered on the polishing platen; a plurality of substrate carriers including a first substrate carrier which moves in a state in which a substrate is mounted and performs a polishing process in a state in which the substrate is in contact with the polishing pad on the polishing pad; a monitoring unit of displaying the information including the identity, position of at least one of the substrate carriers; and a control unit of outputting a warning signal and/or changes the operation of operating devices when an error occurs in real time thereby improving the monitoring efficiency and operation reliability of the polishing process of the substrate.
    Type: Application
    Filed: May 20, 2019
    Publication date: January 9, 2020
    Applicant: KCTECH CO., LTD.
    Inventors: Jong-Tae JOO, Sang Hyun KIM, Ho Cheon JEONG, Jae Yeol KIM
  • Patent number: 10475774
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Publication number: 20190259737
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Application
    Filed: September 18, 2018
    Publication date: August 22, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Patent number: 10342807
    Abstract: The present invention relates to a pharmaceutical composition for preventing, treating or delaying an Alzheimer's disease (AD) or dementia including a G protein-coupled receptor19 (GPCR19) agonist or its pharmaceutically acceptable salt as an active ingredient and a food composition for preventing, treating or delaying an Alzheimer's disease or dementia. The GPCR19 agonist according to the present invention has an effect of improving cognitive and behavioral disorders without harming the health of objects when administrated to the objects and has an effect of preventing the Alzheimer's disease or dementia or delaying or treating the progression of the disease in the objects with the disease by suppressing apoptosis of the brain tissue, enhancing immunity, and reducing formation of an amyloid ? (A?) plague.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 9, 2019
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seung Yong Seong, Jung Ah Cho, Tae Joo Kim, Youn Hee Kim
  • Publication number: 20190160149
    Abstract: A pharmaceutical composition for preventing or treating cartilage diseases, and pharmaceutical preparation that includes the pharmaceutical composition as an active ingredient are provided.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 30, 2019
    Inventors: Tae Joo Park, Eun Kyung Song
  • Publication number: 20190148337
    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.
    Type: Application
    Filed: June 7, 2018
    Publication date: May 16, 2019
    Inventors: Yong-hoon KIM, Kil-soo KIM, Kyung-suk OH, Tae-joo HWANG
  • Publication number: 20190139939
    Abstract: A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Tae Joo HWANG
  • Patent number: 10262967
    Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joo Hwang, Eun-Seok Song
  • Publication number: 20190098923
    Abstract: Disclosed are a novel strain of Bacillus amyloliquefaciens, a method of producing fermented grains using the strain, fermented grains produced using the strain, and a composition for thrombolysis; digestion improvement; prophylaxis, amelioration or treatment of bowel inflammation, serous membrane weakening or intestinal injury; or antioxidation, comprising the fermented grains.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 4, 2019
    Inventors: Min Ju PARK, Ah Jin KIM, Sung Wook HAN, Su Jin HEO, Tae Joo YANG, Seung Won PARK, Sang Bum LEE, Jae Ho JANG, Seong Jun CHO, Young Ho HONG, Sung Hee PARK