Patents by Inventor Tae-jung Lee
Tae-jung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961679Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.Type: GrantFiled: November 2, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Eun Jung Lee, Jong Suk Jeong, Chun Hee Seo, Jong Hoon Yoo, Tae Hyung Kim, Ho Sam Choi, Sim Chung Kang
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Publication number: 20240121987Abstract: A display device includes a substrate; an auxiliary electrode including metal layers stacked in an undercut structure; and a light-emitting element layer. The light-emitting element layer includes a second common layer; and a common electrode which extend to the non-emission area. A side surface of the auxiliary electrode includes a first bonding portion in contact with the second common layer, and a second bonding portion in contact with the common electrode. The auxiliary electrode includes a first side and a second side facing each other in one direction, and a third side and a fourth side facing each other in other direction crossing the one direction. The first bonding portion has a first width at a first point of the first side and has a second width smaller than the first width at a second point of the third side.Type: ApplicationFiled: June 30, 2023Publication date: April 11, 2024Inventors: Yeon Hwa LEE, Duck Jung LEE, Joon Gu LEE, Tae Wook KANG
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Publication number: 20240119851Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.Type: ApplicationFiled: September 29, 2023Publication date: April 11, 2024Inventors: Eun Young LEE, Min Jung KIM, Yeun Hee KANG, Bong Hyun CHOI, Tae Un KIM, Soo Hyun LEE, Young Ho KIM, Chan Kyu CHOI, Jin Mo KU, Jong Won KIM
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Publication number: 20240103958Abstract: A method performed by a managing server includes: receiving, from an electronic device, operation data of the electronic device; identifying, by using artificial intelligence (AI), a device usage pattern of the electronic device; identifying, by using the AI, information related to a failure or an abnormal operation of the electronic device and a solution to the failure or the abnormal operation based on the device usage pattern and the operation data received from the electronic device; and transmitting, to a user terminal, the information related to the failure or the abnormal operation of the electronic device and the solution to the failure or the abnormal operation.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hun LEE, Myung-Sun KIM, Ayush JAIN, Tae-Ho SWANG, Jae-Hong KIM, Hye-Jung CHO
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Publication number: 20240088059Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive spaced-apart pillar structures.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Young Woo LEE, Jae Ung LEE, Byong Jin KIM, EunNaRa CHO, Ji Hoon OH, Young Seok KIM, Jin Young KHIM, Tae Kyeong HWANG, Jin Seong KIM, Gi Jung KIM
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Publication number: 20240090121Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung BYUN, Jung Soo KIM, Sang Hyun SIM, Chang Min HA, Tae Hong MIN, Jin Won LEE
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Patent number: 11930647Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.Type: GrantFiled: August 1, 2022Date of Patent: March 12, 2024Assignee: SK hynix Inc.Inventors: Si Jung Yoo, Tae Hoon Kim, Hyung Dong Lee
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Patent number: 11921456Abstract: An example image forming apparatus includes a frame, a first shaft supported by the frame, and a first coupler. The first coupler includes a body coupled to one end of the first shaft and a first protrusion protruding from the body in an axial direction of the first shaft, the first protrusion having a first surface and a second protrusion protruding from the first surface. The second protrusion is to lock with a groove to mount a cartridge on the frame, the first shaft is to provide a rotational force in a first rotational direction to rotate the second protrusion of the first coupler and to insert the second protrusion into the groove to lock with the cartridge, and the first surface of the first protrusion of the first coupler is to contact a second surface to transmit the rotational force to the second coupler in the first rotational direction.Type: GrantFiled: February 22, 2023Date of Patent: March 5, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Pil-Seung Oh, Taeil Jung, Tae-Hee Kim, Chang-Woo Lee
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Patent number: 11913133Abstract: The present invention relates to a method of manufacturing polycrystalline silicon ingot using a crucible in which an oxygen exhaust passage is formed by single crystal or polycrystalline rods, the method including the steps of: manufacturing the single crystal or polycrystalline silicon rods each having the shape of a quadrilateral pillar; putting the single crystal or polycrystalline quadrilateral pillar-shaped silicon rods into the crucible in such a manner as to be arranged close to one another along the inner peripheral surface of the crucible to thus form a space portion inside the single crystal or polycrystalline silicon rods, into which silicon chunks are put, and the oxygen exhaust passages between the inner peripheral surface of the crucible and the respective surfaces of the single crystal or polycrystalline silicon rods oriented toward the inner peripheral surface of the crucible; putting the silicon chunks into the space portion of the crucible; and melting and crystallizing the silicon chunks.Type: GrantFiled: July 6, 2022Date of Patent: February 27, 2024Assignee: Lintech CorporationInventors: Ho Jung You, Dong Nam Shin, Sei Kwang Oh, Jun Seok Lee, Sun Bin Yum, Tae-Woo Kang
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Patent number: 11913098Abstract: A self-healing alloy contains 5 to 11% by weight of molybdenum (Mo), iron (Fe) as a remainder, and unavoidable impurities. A method for manufacturing the self-healing alloy includes heat treating the alloy or preparing an alloy raw material powder and sintering, homogenizing, and cooling the alloy raw material powder.Type: GrantFiled: March 22, 2021Date of Patent: February 27, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, Kookmin University Industry Academy Cooperation FoundationInventors: Kyung Sik Choi, Hoo Dam Lee, Tae Gyu Lee, Byung Ho Min, Young Jun Kwon, Keun Won Lee, Yoon Jung Won, Ki Sub Cho
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Patent number: 8987797Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.Type: GrantFiled: October 10, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Oh-Kyum Kwon, Tae-Jung Lee, Kyoung-Eun Uhm, Byung-Sun Kim
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Publication number: 20150060318Abstract: The present invention relates to a wrap case (1) for packaging in which a wrap for packaging (3) wound around a branch pipe (2) is accommodated.Type: ApplicationFiled: November 13, 2012Publication date: March 5, 2015Inventor: Tae-Jung Lee
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Patent number: 8652911Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.Type: GrantFiled: July 1, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kee-In Bang, Tae-Jung Lee, Myoung-Kyu Park
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Publication number: 20140035017Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.Type: ApplicationFiled: October 10, 2013Publication date: February 6, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Oh-Kyum Kwon, Tae-Jung Lee, Kyoung-Eun Uhn, Byung-Sun Kim
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Integrated Circuit Devices Including Device Isolation Structures and Methods of Fabricating the Same
Publication number: 20130313654Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Inventors: Oh-kyum Kwon, Tae-jung Lee, Sun-hyun Kim -
Patent number: 8587045Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.Type: GrantFiled: July 13, 2011Date of Patent: November 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Oh-Kyum Kwon, Tae-Jung Lee, Kyoung-Eun Uhn, Byung-Sun Kim
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Integrated circuit devices including device isolation structures and methods of fabricating the same
Patent number: 8525273Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.Type: GrantFiled: January 31, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Oh-kyum Kwon, Tae-jung Lee, Sun-hyun Kim -
Patent number: 8143690Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.Type: GrantFiled: July 21, 2008Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-kyu Park, Byung-sun Kim, Tae-jung Lee, Kee-in Bang
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Publication number: 20120037971Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.Type: ApplicationFiled: July 13, 2011Publication date: February 16, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Oh-Kyum Kwon, Tae-Jung Lee, Kyoung-Eun Uhn, Byung-Sun Kim
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Publication number: 20120032269Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-ryul Chang, Tae-jung Lee, Sung-hoan Kim, Soo-cheol Lee