Abstract: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: This invention relates to a method of preparing cellulose solution which is homogeneous at relatively low temperature, in which a small amount of cellulose powder or polyvinylalcohol is dissolved in the liquid-state, concentrated N-methylmorpholine-N-oxide (hereinafter, referred to as ‘NMMO’) so as to lower the solidifying temperature of NMMO, and then, the resulting solution and cellulose powder are fed into an extruder so as to be mixed, swollen and melted in the extruder.

Abstract: This invention relates to a method of preparing cellulose solution which is homogeneous at relatively low temperature, in which a small amount of cellulose powder or polyvinylalcohol is dissolved in the liquid-state, concentrated N-methylmorpholine-N-oxide (hereinafter, referred to as ‘NMMO’) so as to lower the solidifying temperature of NMMO, and then, the resulting solution and cellulose powder are fed into an extruder so as to be mixed, swollen and melted in the extruder.

Abstract: The present invention relates to an expansion tube that has a plurality of expansion slits on the outer peripheral surface thereof long a longitudinal direction, each of the expansion slits having a predetermined width and a relatively larger length than the predetermined width, and an apparatus for manufacturing a heat shrinkable tube, having the expansion tube, that can regularly and fast expand the heat shrinkable tube, and after the expansion, regularly and fast cool the heat shrinkable tube by the cooling water sprayed through the slits, thereby rapidly and stably manufacturing the heat shrinkable.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a semiconductor substrate, a transistor having a gate interconnection that extends in one direction on the semiconductor substrate and source/drain regions aligned in the gate interconnection and formed in the semiconductor substrate, and a diffusion-preventing metallic pattern extending on the gate interconnection in the same direction as the gate interconnection and which prevents ions from being diffused into the semiconductor substrate.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

Abstract: The present invention relates to a method for making highly homogenized cellulose solution, wherein the cellulose solution is obtained by obtaining a solidified N-methylmorphorine-N-oxide (hereinafter, referred to as ‘NMMO’) hydrates which is solidified a liquid-state NMMO hydrates comprising 10 to 18% by weight water by using a simple screw-type feeder and by controlling the temperature, feeding the solidified NMMO into a twin-screw type extruder continuously, obtaining a cellulose solution which is fully swelled in a few minutes by dispersing and mixing with cellulose powder in the twin-screw type extruder, and extruding a highly homogenized cellulose solution by feeding the obtained cellulose solution into a melting zone of the extruder to melting the cellulose solution in a few minutes by minimum heat and shear force.

Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.

Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.

Abstract: There is provided with a cellulose fiber suitable for industrial material which is produced by a process comprising following steps: producing NMMO solution made in a manner to dissolve 0.1 wt % to 10 wt % of salt and polyvinyl alcohol in concentrated N-Methyl Morpholine N-oxide (NMMO) in liquid state; producing cellulose solution in a manner that said NMMO solution is mixed with cellulose powder and then said cellulose powder is swelled to produce cellulose solution; obtaining multifilament by solidifying said cellulose solution reached at a coagulation bath through air layer after extruded-sprayed with spraying nozzle having orifices of 500 to 2000; and winding said multifilament for storing after in turn washing, drying and treating with organic solvent, and the cellulose fiber according to the present invention is suitable for industrial materials due to excellent mechanical strength.

Abstract: The present invention relates to cellulose fiber containing 500 to 2000 of filaments and having homogeneous physical properties and the multi-filaments according to the present invention is characterized in that the strength and the breaking elongation of the multi-filaments are 4 to 9 g/d and 4 to 15%, respectively. In particular, the present invention is characterized in that each mono-filament selected 100 strands from every three part divided from multi-filaments has properties as following: (a) 3 to 9 g/d in average strength, 7 to 15% in average breaking elongation and 0.035 to 0.055 in by birefringence, (b) the differences of the above three parts are below 1.0 g/d in average strength, 1.5% in breaking elongation and 0.7 denier in denier, (c) the CV (%)(coefficient of variation) of the above three parts are below 10%, and (d) the birefringence differences of the above three parts are below 0.004.

Abstract: A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

Abstract: The present invention relates to a method for making highly homogenized cellulose solution, wherein the cellulose solution is obtained by obtaining a solidified N-methylmorphorine-N-oxide (hereinafter, referred to as ‘NMMO’) hydrates which is solidified a liquid-state NMMO hydrates comprising 10 to 18% by weight water by using a simple screw-type feeder and by controlling the temperature, feeding the solidified NMMO into a twin-screw type extruder continuously, obtaining a cellulose solution which is fully swelled in a few minutes by dispersing and mixing with cellulose powder in the twin-screw type extruder, and extruding a highly homogenized cellulose solution by feeding the obtained cellulose solution into a melting zone of the extruder to melting the cellulose solution in a few minutes by minimum heat and shear force.

Abstract: This invention relates to a method of preparing cellulose solution which is homogeneous at relatively low temperature, in which a small amount of cellulose powder or polyvinylalcohol is dissolved in the liquid-state, concentrated N-methylmorpholine-N-oxide (hereinafter, referred to as ‘NMMO’) so as to lower the solidifying temperature of NMMO, and then, the resulting solution and cellulose powder are fed into an extruder so as to be mixed, swollen and melted in the extruder.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.