Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

Abstract: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Abstract: An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

Abstract: The present invention relates to a cellulose fiber having a highly homogeneous section, particularly to a cellulose fiber with lower Coefficient of Variation of section diameter (CV(%)). Specifically, the present invention relates to a cellulose fiber wherein Coefficient of Variation of section diameter (CV(%)) of a mono-filament constituting a multi-filament prepared by dissolving a cellulose powder in liquid N-methylmorpholine N-oxide (hereinafter referred to “NMMO”) is below 2.5. According to the present invention, a lyocell multi-filament is produced comprising the steps of (i) preparing a spinning solution by homogeneously dispersing, swelling and dissolving cellulose powder in a NMMO solution; (ii) spinning the spinning solution into an air gap through a spinning nozzle; and (iii) coagulating the extruded-spun spinning solution in a coagulation bath. In particular, the coagulating step is adjusted by means of a coagulation coefficient in the range of 0.8 to 1.

Abstract: The present invention relates to cellulose fiber containing 500 to 2000 of filaments and having homogeneous physical properties and the multi-filaments according to the present invention is characterized in that the strength and the breaking elongation of the multi-filaments are 4 to 9 g/d and 4 to 15%, respectively. In particular, the present invention is characterized in that each mono-filament selected 100 strands from every three part divided from multi-filaments has properties as following: (a) 3 to 9 g/d in average strength, 7 to 15% in average breaking elongation and 0.035 to 0.055 in by birefringence, (b) the differences of the above three parts are below 1.0 g/d in average strength, 1.5% in breaking elongation and 0.7 denier in denier, (c) the CV (%) (coefficient of variation) of the above three parts are below 10%, and (d) the birefringence differences of the above three parts are below 0.004.

Abstract: A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump.

Abstract: The present invention relates to cellulose fiber containing 500 to 2000 of filaments and having homogeneous physical properties and the multi-filaments according to the present invention is characterized in that the strength and the breaking elongation of the multi-filaments are 4 to 9 g/d and 4 to 15%, respectively. In particular, the present invention is characterized in that each mono-filament selected 100 strands from every three part divided from multi-filaments has properties as following: (a) 3 to 9 g/d in average strength, 7 to 15% in average breaking elongation and 0.035 to 0.055 in by birefringence, (b) the differences of the above three parts are below 1.0 g/d in average strength, 1.5% in breaking elongation and 0.7 denier in denier, (c) the CV (%) (coefficient of variation) of the above three parts are below 10%, and (d) the birefringence differences of the above three parts are below 0.004.

Abstract: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract: The present invention provides a lyocell raw cord prepared from at least 2-ply lyocell multifilaments, which gives a stress-strain curve exhibiting that (a) the lyocell raw cord has an elongation of 1.5% or less at an initial stress of 1.0 g/d, and an initial modulus value of 50 to 100 g/d; (b) has an elongation of 7% or less in a stress region of 1.0 g/d to 4.0 g/d; and (c) has an elongation of 1% or more at a tensile strength of 4.0 g/d to the breaking point, as measured in the dried state. The lyocell raw cord prepared according to the present invention can be used as industrial fibers, in particular, fibers for tire cords.

Abstract: A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing gate line commonly connected to the memory cells.

Abstract: An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

Abstract: The present invention relates to cellulose fiber containing 500 to 2000 of filaments and having homogeneous physical properties and the multi-filaments according to the present invention is characterized in that the strength and the breaking elongation of the multi-filaments are 4 to 9 g/d and 4 to 15%, respectively. In particular, the present invention is characterized in that each mono-filament selected 100 strands from every three part divided from multi-filaments has properties as following: (a) 3 to 9 g/d in average strength, 7 to 15% in average breaking elongation and 0.035 to 0.055 in by birefringence, (b) the differences of the above three parts are below 1.0 g/d in average strength, 1.5% in breaking elongation and 0.7 denier in denier, (c) the CV (%) (coefficient of variation) of the above three parts are below 10%, and (d) the birefringence differences of the above three parts are below 0.004.

Abstract: A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.

Abstract: The present invention relates to a method for producing a cellulose solution which is homogeneous at low temperatures, and to fiber produced by the method. More particularly, the invention relates to a production of a cellulose solution which is homogeneous at low temperatures, by dissolving a small amount of the cellulose powder in concentrated liquid N-methylmorpholine-N-oxide (NMMO) to lower the solidification temperature of NMMO, introducing the low-temperature, concentrated liquid NMMO solution having cellulose dissolved and the cellulose powder into a kneader, mixing and swelling the cellulose in the kneader without a process of reducing pressure to produce a paste, and then supplying the paste into an extruder to dissolve the paste in a homogeneous solution.