Abstract: A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to a temperature sense driving signal, a power supply selecting unit for driving a driving voltage supply terminal to one of different voltage levels according to the plurality of temperature sensing signals, and an internal refresh signal generating unit for receiving a driving voltage from the power supply selecting unit and producing internal refresh signals at a constant interval.

Abstract: Disclosed is a system for displaying and managing information on a webpage using an indicator in which, a memo and so forth can be recorded in the desired contents of the webpage through the indicator and the URL of the webpage can be stored with the indicator to call out them at anytime, whereby providing a convenience in terms of search and manage of information.

Abstract: An ink-jet printhead and a manufacturing method thereof include a substrate on which a space portion is formed, a passage plate installed on the substrate in which an ink chamber is formed to store ink, a nozzle plate installed at a top surface of the passage plate in which a nozzle is formed to eject the ink, and a vibration plate disposed between the substrate and the passage plate to generate a pressure for ejecting the ink by changing a volume of the ink chamber.

Abstract: A monitoring system using a real-time simulator, providing a simulation environment of a real electric power system that enables testing of a new electric power system control facility. The operation of the new electric power system control facility and effects thereof on a real electric power system can be evaluated before actual installation. The monitoring system includes a test piece installed in an electric power system; a simulator connected to the test piece, and deriving electric power system simulation data by simulating the electric power system with respect to the test piece; a multimedia interface (MMI) platform interworking with the simulator, providing the simulator with electric power system status data for simulating the electric power system, and receiving the electric power system simulation data from the simulator; and an MMI client interworking with the MMI platform to display the electric power system simulation data from the MMI platform.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: The present invention relates to an acyclic nucleoside phosphonate derivative which is useful as an antiviral agent (particularly, against hepatitis B virus), pharmaceutically acceptable salts, stereoisomers, and a process for the preparation thereof.

Abstract: Provided is an optimized system voltage control method through coordinated control of reactive power source, which analyzes the location for reactive power compensation and the effect of applying compensation equipment by calculating the reactive power and voltage sensitivity of a power system, thus improving the voltage quality of the power system.

Abstract: Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier.

Abstract: A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.

Abstract: Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A recess is defined by etching the nitride layer. A metal nitride layer is formed in the recess in an U shape, and then a metal layer is formed to bury the recess. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier.

Abstract: An image forming apparatus including a power supply unit which supplies high voltage AC power, a developing unit having at least one developing roller to receive first AC power from the power supply unit to supply a developer to an image receptor, and an erasing unit to receive second AC power to attenuate high frequency noise of the developing unit.

Abstract: The present invention relates to an acyclic nucleoside phosphonate derivative which is useful as an antiviral agent (particularly, against hepatitis B virus), pharmaceutically acceptable salts, stereoisomers, and a process for the preparation thereof.

Abstract: Disclosed herein are an electrically conductive thermoplastic resin composition and a plastic article including the same. The electrically conductive thermoplastic resin composition comprises about 80 to about 99.9 parts by weight of a thermoplastic resin, about 0.1 to about 10 parts by weight of carbon nanotubes, about 0.1 to about 10 parts by weight of an impact modifier, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes, and about to about 10 parts by weight of conductive metal oxide, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes.

Abstract: The present invention relates to an acyclic nucleoside phosphonate derivative represented by the following formula (1): in which represents single bond or double bond, R1, R2, R3, R7 and R8 are defined herein, Y represents —O—, —S—, —CH(Z)-, ?C(Z)-, —N(Z)-, ?N—, or —SiH(Z)-, wherein Z represents hydrogen, hydroxy or halogen, or represents C1-C7-alkyl, C1-C5-alkoxy, allyl, hydroxy-C1-C7-alkyl, C1-C7-aminoalkyl or phenyl, Q represents a group having the following formula: wherein X1, and X2 independently of one another represent hydrogen, amino, hydroxy or halogen, or represent C1-C7-alkyl, C1-C5-alkoxy, allyl, hydroxy-C1-C7-alkyl, phenyl or phenoxy each of which is optionally substituted by nitro or C1-C5-alkoxy, or represent C6-C10-arylthio which is optionally substituted by nitro, amino, C1-C6-alkyl or C1-C4-alkoxy, or represent C6-C12-arylamino, C1-C7-alkylamino, di(C1-C7-alkyl)amino, C3-C6-cycloalkylamino or a structure of wherein n denotes an integer of 1 or 2 and Y1 represents O, CH2 or N—

Abstract: An inkjet print head including a substrate and a first film member stacked on the substrate to form an ink path, and a manufacturing method thereof. The first film member includes a path-defining layer made of a photosensitive material and formed with the ink path, and an adhesive layer made of a photosensitive material and used to stably bond the path-defining layer to the substrate. With this configuration, the path-defining layer and the adhesive layer can be simultaneously stacked on the substrate and also, can be patterned simultaneously.

Abstract: A method and apparatus of dot counting. The apparatus includes a nozzle portion having a length corresponding to a width of a printing medium, a dot counting unit to group head nozzles by position and to count a discharged dot count per line for each group, a control unit to determine whether the group has been used to print using the discharged dot count per line, a counter to count a number of times that the group is used to print based on the determination result, and a memory to store a sum of the counted numbers of times, in which the control unit controls the counter to count the number of times that the group is used to print with respect to each line of image data when the image data is created by a head chip, and a sum of the counted number of times is stored in the memory.

Abstract: An ink cartridge to prevent image degradation due to a misalignment of nozzles in a transfer direction of a printing medium and a transverse direction includes a print head substrate, a first head unit including at least one first print head chip which is disposed on the print head substrate and includes a plurality of first nozzles arranged in plural lines in a second direction perpendicular to a first direction which is a transfer direction of a printing medium, thereby forming a first line in the second direction, and a second head unit including at least one second print head chip which is disposed on the print head substrate and which has an ink jetting area overlapping a predetermined area of the first line, thereby forming an overlapping area, and which includes a plurality of second nozzles arranged in plural lines in the second direction, thereby forming a second line spaced from the first line, and dots formed by the first and the second nozzles, which neighbor each other in the overlapping area whe