Abstract: An apparatus and method for simplifying 3-Dimensional (3D) mesh data are disclosed. The method includes measuring discrete curvature at each point of received 3D mesh data, calculating an error based on distance-curvature error metrics including the discrete curvature, first sorting a low curvature one of the calculated error values in a heap in ascending order, selecting a minimum error among the calculated errors, determining if the minimum error is less than a threshold, contracting an edge if the selected minimum error is greater than the threshold, and recalculating an error of a surface neighboring to a surface on which the contracted edge belongs and re-sorting the calculated error values.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A thermal inkjet printhead that includes a substrate, a chamber layer stacked on the substrate, an ink chamber formed in the chamber layer, a heater to heat ink filled in the ink chamber to generate bubbles, and a nozzle layer stacked on the chamber layer, and including a nozzle formed in the nozzle layer, wherein a ratio of the volume of ink ejected through the nozzle with respect to the sum of the volumes of the ink chamber and the nozzle is in the range of approximately 40 to 60%.

Abstract: A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: Disclosed herein are an electrically conductive thermoplastic resin composition and a plastic article including the same. The electrically conductive thermoplastic resin composition comprises about 80 to about 99.9 parts by weight of a thermoplastic resin, about 0.1 to about 10 parts by weight of carbon nanotubes, about 0.1 to about 10 parts by weight of an impact modifier, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes, and about 0.1 to about 10 parts by weight of conductive metal oxide, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: An ink cartridge to prevent image degradation due to a misalignment of nozzles in a transfer direction of a printing medium and a transverse direction includes a print head substrate, a first head unit including at least one first print head chip which is disposed on the print head substrate and includes a plurality of first nozzles arranged in plural lines in a second direction perpendicular to a first direction which is a transfer direction of a printing medium, thereby forming a first line in the second direction, and a second head unit including at least one second print head chip which is disposed on the print head substrate and which has an ink jetting area overlapping a predetermined area of the first line, thereby forming an overlapping area, and which includes a plurality of second nozzles arranged in plural lines in the second direction, thereby forming a second line spaced from the first line, and dots formed by the first and the second nozzles, which neighbor each other in the overlapping area whe

Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.

Abstract: Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier.

Abstract: Provided are an apparatus and method for providing security for an image signal in a base station or a terminal by detecting face information from the image signal. The apparatus includes a signal receiving unit receiving an image signal transmitted from a terminal, a location discriminating unit detecting a calling location of the terminal and checking if the calling location falls within a security region, and a controller transmitting the image signal when the calling location does not fall within the security region, or when the calling location falls within the security region and the image signal contains face information. Accordingly, it is possible to prevent unauthorized transmission of images without additional big burden of security equipment or an invasion of individual rights of using image communication.

Abstract: A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.