Abstract: The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT4 receptor agonist, and therefore can be usefully applied for preventing or treating dysfunction in gastrointestinal motility, one of the gastrointestinal diseases, such as gastroesophageal reflux disease (GERD), constipation, irritable bowel syndrome (IBS), dyspepsia, post-operative ileus, delayed gastric emptying, gastroparesis, intestinal pseudo-obstruction, drug-induced delayed transit, or diabetic gastric atony.

Abstract: A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect path to the target internal circuit that is longer than the direct path in response to one or more path control signals and use the selected path when the data signal is transmitted between the I/O circuit and the plurality of internal circuits.

Abstract: A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: An inkjet print head including a substrate and a first film member stacked on the substrate to form an ink path, and a manufacturing method thereof. The first film member includes a path-defining layer made of a photosensitive material and formed with the ink path, and an adhesive layer made of a photosensitive material and used to stably bond the path-defining layer to the substrate. With this configuration, the path-defining layer and the adhesive layer can be simultaneously stacked on the substrate and also, can be patterned simultaneously.

Abstract: A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.

Abstract: Provided is an optimized system voltage control method through coordinated control of reactive power source, which analyzes the location for reactive power compensation and the effect of applying compensation equipment by calculating the reactive power and voltage sensitivity of a power system, thus improving the voltage quality of the power system.

Abstract: A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.

Abstract: A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.

Abstract: A monitoring system using a real-time simulator, providing a simulation environment of a real electric power system that enables testing of a new electric power system control facility. The operation of the new electric power system control facility and effects thereof on a real electric power system can be evaluated before actual installation. The monitoring system includes a test piece installed in an electric power system; a simulator connected to the test piece, and deriving electric power system simulation data by simulating the electric power system with respect to the test piece; a multimedia interface (MMI) platform interworking with the simulator, providing the simulator with electric power system status data for simulating the electric power system, and receiving the electric power system simulation data from the simulator; and an MMI client interworking with the MMI platform to display the electric power system simulation data from the MMI platform.

Abstract: An apparatus and method for simplifying 3-Dimensional (3D) mesh data are disclosed. The method includes measuring discrete curvature at each point of received 3D mesh data, calculating an error based on distance-curvature error metrics including the discrete curvature, first sorting a low curvature one of the calculated error values in a heap in ascending order, selecting a minimum error among the calculated errors, determining if the minimum error is less than a threshold, contracting an edge if the selected minimum error is greater than the threshold, and recalculating an error of a surface neighboring to a surface on which the contracted edge belongs and re-sorting the calculated error values.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.