Abstract: A display device includes a display unit comprising a plurality of pixels. A touch sensing unit is disposed on the display unit and comprises a plurality of driving electrodes and a plurality of sensing electrodes. A touch driver supplies a touch driving signal to the driving electrodes through a plurality of driving lines and receives a touch sensing signal from the sensing electrodes through a plurality of sensing lines. During a first horizontal period of one frame period, the touch driver supplies a touch driving signal having a first pulse width to a first partial portion of the driving lines and supplies a touch driving signal having a second pulse width smaller than the first pulse width to a second partial portion of the driving lines that is different from the first partial portion of the driving lines.

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.

Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.

Abstract: A package substrate, including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer, and a multi-chip package, including the package substrate, are provided.

Abstract: A printed circuit board includes a core layer having a first through-portion, a coil structure disposed in the first through-portion and comprising a support member, a first coil pattern in a planar spiral form disposed on one surface of the support member, and a body comprising a magnetic substance, wherein the support member and the first coil pattern are accommodated in the body, a first build-up layer covering at least a portion the core layer and disposed in at least a portion of the first through-portion, a first wiring layer disposed on one surface of the first build-up layer, and a first via layer passing through at least a portion of the first build-up layer and connected to the first wiring layer. The first via layer comprises a first wiring via connecting at least a portion of the first wiring layer to the first coil pattern.

Abstract: A makeup evaluation system can include a mobile terminal for photographing an image and transmitting the photographed image to a makeup server; and a makeup server including a make-up DB management unit for storing at least one algorithm used for make-up evaluation, a region detection unit for detecting a face region in the photographed image, a makeup analysis unit for evaluating makeup by applying the stored algorithm to the detected face region, and a wireless communication unit for transmitting an evaluation result signal including information on the result of evaluating the makeup to the mobile terminal, in which the mobile terminal displays the evaluation result according to a received evaluation result signal, and the makeup server evaluates makeup by applying different algorithms for each face region.

Abstract: A printed circuit board assembly includes a first printed circuit board, a second printed circuit board, and a space holding member. The second printed circuit board includes a first rigid substrate region, spaced apart from and opposed to the first printed circuit board, and a flexible substrate region, extended from one side of the first rigid substrate region to be connected to the first printed circuit board. The space holding member includes a first member, disposed between the first printed circuit board and the second printed circuit board to maintain a space therebetween, and a second member configured to fix the first printed circuit board or the second printed circuit board on the first member.

Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

Abstract: A makeup evaluation system according to an embodiment of the present invention includes a mobile terminal for photographing a facial image and transmitting the photographed facial image to a makeup server, and the makeup server for storing makeup score data and, when receiving the facial image from the mobile terminal, detecting at least one face region in the facial image, calculating a makeup score for each of the detected face regions on the basis of the makeup score data, and transmitting the calculated makeup score to the mobile terminal.

Abstract: A printed circuit board includes a core layer having a through portion, a magnetic member disposed in the through portion and comprising a magnetic layer, a first coil pattern attached to one surface of the magnetic layer via an adhesive, and a first build-up layer covering at least a portion of the core layer, at least a portion of the magnetic member, and at least a portion of the first coil pattern, and disposed in at least a portion of the through portion.

Abstract: A component mounting board includes first and second substrates, a connection substrate, an interposer, and an electronic component. The first substrate has first and second surfaces opposing each other, a first side surface between the first and second surfaces, and a first signal pattern. The second substrate is disposed on the first substrate, has third and fourth surfaces opposing each other and a second side surface between the third and fourth surfaces, and includes a second signal pattern. The connection substrate is bent to connect the first and second side surfaces, and the interposer is disposed between the first and third surfaces and electrically connects the first and second signal patterns. The electronic component is mounted on at least one of the first to fourth surfaces.

Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

Abstract: An electronic component embedded substrate includes a core member including a first wiring layer, a first insulating layer covering the first wiring layer and having a first through-portion, a second wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and having a second through-portion exposing at least a portion of the second wiring layer; a first electronic component disposed in the first through-portion; a second electronic component disposed in the second through-portion; and an insulating resin covering at least a portion of each of the first electronic component and the second electronic component. The second wiring layer includes a first wiring pattern having a portion covered with the second insulating layer, and a second wiring pattern having a portion covered with the insulating resin. The second electronic component is connected to the second wiring pattern.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.